Search for: All records

The precision metrology of through-hole silicon via (TSV) in the semiconductor industry has remained a critical challenge as its critical dimension (CD) reduces. In this letter, we report a novel method for TSV geometric feature measurement and characterization. By illuminating a collimated infrared laser beam to the TSV and then analyzing the TSV edge-induced diffraction interferometric fringe patterns, multiple geometric information of the TSV could be characterized, establishing its database. This computational approach to TSV characterization was validated by experiments. Being non-destructive and easy to deploy, this method provides a low cost and high efficiency solution for TSV metrology. 

In smart manufacturing, semiconductors play an indispensable role in collecting, processing, and analyzing data, ultimately enabling more agile and productive operations. Given the foundational importance of wafers, the purity of a wafer is essential to maintain the integrity of the overall semiconductor fabrication. This study proposes a novel automated visual inspection (AVI) framework for scrutinizing semiconductor wafers from scratch, capable of identifying defective wafers and pinpointing the location of defects through autonomous data annotation. Initially, this proposed methodology leveraged a texture analysis method known as gray-level co-occurrence matrix (GLCM) that categorized wafer images—captured via a stroboscopic imaging system—into distinct scenarios for high- and low-resolution wafer images. GLCM approaches further allowed for a complete separation of low-resolution wafer images into defective and normal wafer images, as well as the extraction of defect images from defective low-resolution wafer images, which were used for training a convolutional neural network (CNN) model. Consequently, the CNN model excelled in localizing defects on defective low-resolution wafer images, achieving an F1 score—the harmonic mean of precision and recall metrics—exceeding 90.1%. In high-resolution wafer images, a background subtraction technique represented defects as clusters of white points. The quantity of these white points determined the defectiveness and pinpointed locations of defects on high-resolution wafer images. Lastly, the CNN implementation further enhanced performance, robustness, and consistency irrespective of variations in the ratio of white point clusters. This technique demonstrated accuracy in localizing defects on high-resolution wafer images, yielding an F1 score greater than 99.3%. 

This paper introduces a new digital integration that combines edge diffractometry with convolutional neural networks (CNN) for via metrology and inspection. The beam propagation method (BMP) was used to simulate the interferogram generated by edge diffractometry to characterize via edge roughness (VER). A comprehensive database was established to link different fringe patterns to VER for CNN training. The well-trained CNN-based methodology provided a fast and accurate assessment of VER, with a root mean squared error (RMSE) of 0.073 and an average mean absolute deviation ratio (MADR) of 2.274%. In addition, the proposed digital approach was compared to the multilayer perceptron machine (MLP) in terms of computational efficiency and predictive accuracy. The proposed digital integration greatly improved the accuracy and speed of VER measurement, characterization, and quantification, potentially enhancing device yield and reliability. The successful application of this digital approach could open up possibilities for various types of via or pattern metrology.