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1. A multiphase switched capacitor power amplifier in 130nm CMOS

   https://doi.org/10.1109/RFIC.2016.7508288  

   Yuan, Wen; Walling, Jeffrey S (May 2016, 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC))

   This paper presents a multiphase switched-capacitor power amplifier (MP-SCPA). Cartesian combining architectures suffer reduced output power and efficiency owing to combination of out-of-phase signals. The multiphase architecture reduces the phase difference between the basis vectors that are combined, increasing the output power and efficiency compared to the Cartesian combiners. 16 equally spaced phases are produced by a phase generator with each phase's relative amplitude weighted on the bottom plate of a capacitor array and combined on a common top plate, resulting in linear amplification. The MP-SCPA delivers a peak output power and PAE of 26 dBm and 24.9%, respectively. When amplifying an LTE signal the average output power and PAE are 20.9 dBm and 15.2%, respectively while achieving <¿¿¿30 dBc ACLR and 3.5 %-rms EVM. 

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2. A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology

   https://doi.org/10.1109/LSSC.2024.3426336  

   Ibrahim, Yahia; Niknejad, Ali (January 2024, IEEE Solid-State Circuits Letters)

   This paper introduces a W-band sequential power amplifier (PA) \cite{0th} with a novel output network designed to minimize passive and combiner losses, while reducing the overall footprint compared to conventional sequential and Doherty PAs\cite{1st}. An isolated output combiner sums two PAs operating in two different modes: the main amplifier operates in class AB and the auxiliary amplifier operates in class C. The measured PA achieves a saturated output power ($$\mathbf{P_{sat}}$$) of 13 dBm and a gain of 12.5 dB with 3 dB bandwidth from 79.5 GHz to 94.5 GHz. Additionally, it demonstrates a peak Power Added Efficiency (PAE) of 19.4\% and a 14.6\% PAE at 6 dB power back-off (PBO) at 87.5 GHz. Furthermore, the PA achieves a data rate of 12 Gb/s for a 16QAM signal with an average output power of 5 dBm, an average PAE of 10\%, and an EVM (RMS) of -20 dB. The PA was fabricated in 16-nm FinFet technology with core area of 0.15mm$^2$. To the authors’ knowledge, this PA has the highest PAE at 6dB PBO for CMOS PAs operating in the W-Band. 

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3. A 28-GHz Hybrid Beamforming Transmitter With Spatial Notch Steering Enabling Concurrent Dual Data Streams for 5G MIMO Applications

   Hu, Yaolong; Zhang, Xiaohan; Chi, Taiyun (May 2024, IEEE journal of solidstate circuits)

   This article presents a new notch steering scheme for hybrid beamforming transmitters (TXs) aimed at suppressing spatial interference, thereby enhancing the signal-to-interference-plus-noise ratio (SINR) to support spatial multiplexing. Built upon existing phased arrays, this scheme integrates an auxiliary-path vector modulator (VM) into each antenna element, which in turn, forms an interference-canceling beam. By spatially combining the array factors (AFs) of the main beam and the interference-canceling beam, a deep spatial notch is created while ensuring minimal main-beam power degradation. Unlike the conventional zero-forcing method that requires matrix inversion in digital for spatial notch creation, our scheme enables the computation of antenna weights in analog, significantly reducing the computational cost and latency. Leveraging this new notch steering scheme, we develop a 28-GHz four-element fully connected (FC) hybrid beamforming TX array using the GlobalFoundries 45-nm CMOS Silicon-on-Insulator (SOI) process. It is capable of simultaneously transmitting two independent, wideband data streams (DSs) in the same polarization toward two directions. In probing-based measurements, each TX channel delivers 19.7-dBm OP1 dB, 20.4-dBm PSAT , and 30.6% peak power-added efficiency (PAE) at 29 GHz, demonstrating state-of-the-art TX linearity and efficiency. In over-the-air (OTA) measurements, the packaged TX array achieves 29.8-dBm EIRP1 dB and is able to steer a spatial notch outside the −10-dB beamwidth of the main beam, with a notch depth of >35 dB and a main-beam power degradation of < 0.8 dB. Moreover, in spatial multiplexing demonstrations, the TX array is capable of transmitting a 400-MHz 64-quadrature amplitude modulation (QAM) signal to the intended receiver (RX) in the first DS, while suppressing the co-channel continuous-wave or wideband modulated interference created by the second DS with a high SINR. 

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4. Efficient wideband RF/mm-wave-to-optical signal transduction by a monolithic CMOS LNA and photonic molecule modulator

   Zhang, Xinchang; Oh, Hyeong_Seok; Singh, Manuj; Wang, Ruocheng; Khodkumbhe, Awani; Li, Ruifu; Cabric, Danijela; Niknejad, Ali M; Chien, Jun-Chau; Stojanović, Vladimir; et al (May 2025, Optica Publishing Group)

   We show efficient wide-tunable mm-wave-to-optical transduction (20 to 70 GHz at -9 to -18 dBc) using a triple-microring modulator. Integrated monolithically with a 18% bandwidth LNA, it generates sidebands with <−35 dBm RF input. 

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5. A Compact Single-Ended Common-Base Doherty PA in 90-nm BiCMOS With 37.3% Peak PAE for 5G Beamforming Arrays

   https://doi.org/10.1109/TMTT.2024.3432602  

   Ali_Mokri, Mohammad; Afshar, Emad; Aminul_Hoque, Md; Miraslani, Soodeh; Mirabbasi, Shahriar; Heo, Deukhyoun (January 2025, IEEE Transactions on Microwave Theory and Techniques)

   This article presents a back-off efficient power amplifier (PA) for mm-wave 5G and upcoming 6G beamforming phased array transceivers (PATs), incorporating advanced circuit designs and novel implementations in both passive and active components. Conventional back-off efficient PAs in the mm-wave frequency range occupy a large chip area, making it hard to fit them into PATs. To overcome this issue, we propose a compact back-off efficient Doherty PA (DPA) with a common base (CB) structure as the core of the PA and small low-loss passive elements. In addition, the proposed architecture moves the role of the input hybrid coupler to the interstage matching network while maintaining DPA functionality. The interstage matching provides the required phases for the main and auxiliary PAs, power division, and impedance matching. The PA prototype is fabricated in the GlobalFoundries 90-nm BiCMOS (9 HP) process. It achieves a peak gain of 20.4 dB at 28.45 GHz with a 1-dB bandwidth of 4.45 GHz. Under large-signal conditions, it archives >19.5-dBm Psat with >36% PAEsat. Its P1dB at 26, 28, and 30 GHz are 19.4, 19.3, and 19.3 dBm with 38.5%, 37.3%, and 36.8% PAE1 dB, respectively. In the 6-dB power back-off region, it reaches efficiencies of 29.1%, 31.1%, and 29.3% at 26, 28, and 30 GHz, respectively. When tested with the NR-FR2 test model at these frequencies, the PA achieves Pavg of 8.25, 8.45, and 8 dBm, and PAEavg of 13.9%, 14.5%, and 13.7% for a 400 M 1-CC 64-QAM signal, maintaining an rms error vector magnitude (EVMrms) of −25.8, −25.8, and −25.7 dB. In addition, in adjacent channel power ratio (ACPR) tests, the PA achieves −27, −26.2, and −30.8 dBc on the lower side and −28.4, −28.5, and −27.6 dBc on the higher side channels at 26, 28, and 30 GHz, respectivelyNot Available 

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