Power devices are highly desirable to possess excellent avalanche and short-circuit (or surge-current) robustness for numerous power electronics applications like automotive powertrains, electric grids, motor drives, among many others. Current commercial GaN power device, the lateral GaN high-electron-mobility transistor (HEMT), is known to have no avalanche capability and very limited short-circuit robustness. These limitations have become a roadblock for penetration of GaN devices in many industrial power applications. Recently, through collaborations with NexGen Power Systems (NexGen), Inc., we have demonstrated breakthrough avalanche, surge-current and short-circuit robustness in NexGen’s vertical GaN p-n diodes and fin-shape junction-gate field-effect-transistors (Fin-JFETs). These large-area GaN diodes and Fin-JFETs were manufactured in NexGen’s 100 mm GaN-on-GaN fab. The demonstrated avalanche, surge-current and short-circuit capabilities are comparable or even superior to Si and SiC power devices. Additionally, vertical GaN Fin-JFETs were found to fail to open-circuit under avalanche and short-circuit conditions, which is highly desirable for the system safety. This talk reviews the key robustness results of vertical GaN power devices and unveils the enabling device physics. Fundamentally, these results signify that, in contrast to some popular belief, GaN devices with appropriate designs can achieve excellent robustness and thereby encounter no barriers for applications in electric vehicles, grids, renewable processing, and industrial motor drives.
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Second Breakdown and Robustness of Vertical and Lateral GaN Power Field‐Effect Transistors
Robustness of GaN power field‐effect transistors, including the vertical UMOSFET, vertical DMOSFET, and lateral p‐AlGaN gate HEMT is studied by analyzing their safe operating areas (SOA) using finite‐element‐analysis device simulation. At off‐state gate voltages, the devices are forced into high‐voltage, high‐current avalanche breakdown. Assuming isothermal conditions at 300 K, the simulated DMOSFET SOA exhibits high robustness, while the UMOSFET and the p‐AlGaN gate HEMT experiences current snapback. The simulated robustness of both the DMOSFET and the UMOSFET degrades when realistic temperature dependence is included in the non‐isothermal case, with current filamentation in high dissipation areas, leading to a more pronounced current snapback.
- NSF-PAR ID:
- 10044605
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- physica status solidi (a)
- Volume:
- 214
- Issue:
- 12
- ISSN:
- 1862-6300
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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