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1. Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

   https://doi.org/10.1038/s41699-022-00353-1  

   Song, Jingfeng ; Qi, Yubo ; Xiao, Zhiyong ; Wang, Kun ; Li, Dawei ; Kim, Seung-Hyun ; Kingon, Angus I. ; Rappe, Andrew M. ; Hong, Xia ( November 2022 , npj 2D Materials and Applications)

   The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS₂transistors back-gated by single-layer polycrystalline PbZr_0.35Ti_0.65O₃. The devices exhibit current switching ratios up to 8 × 10⁶within an ultra-low gate voltage window of$$V_{{{\mathrm{g}}}} = \pm \! 0.5$$$V_g=\pm 0.5$V and subthreshold swing (SS) as low as 9.7 mV decade⁻¹at room temperature, transcending the 60 mV decade⁻¹Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.

    

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2. SnSe/MoS 2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

   https://doi.org/10.1002/adma.201902962  

   Guo, Jian ; Wang, Laiyuan ; Yu, Yiwei ; Wang, Peiqi ; Huang, Yu ; Duan, Xiangfeng ( October 2019 , Advanced Materials)

   The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal‐oxide‐semiconductor field‐effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec⁻¹at room temperature). However, another type of transistor, the junction field‐effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS₂van der Waals (vdW) heterostructure‐based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS₂vdW heterostructure exhibits excellent p–n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS₂as the channel, the SnSe/MoS₂vdW heterostructure exhibit well‐behavioured n‐channel JFET characteristics with a small pinch‐off voltageV_Pof −0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec⁻¹and high ON/OFF ratio over 10⁶, demonstrating excellent electronic performance especially in the subthreshold regime.

    

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3. Engineering the interface chemistry for scandium electron contacts in WSe 2 transistors and diodes

   https://doi.org/10.1088/2053-1583/ab2c44  

   Smyth, Christopher M. ; Walsh, Lee A. ; Bolshakov, Pavel ; Catalano, Massimo ; Schmidt, Michael ; Sheehan, Brendan ; Addou, Rafik ; Wang, Luhua ; Kim, Jiyoung ; Kim, Moon J. ; et al ( July 2019 , 2D Materials)

   Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS₂, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe₂transistors with impressive subthreshold slope (109 mV dec⁻¹) andI_ON/I_OFF(10⁶) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe₂in situbefore metallization, which minimizes subsequent reactions between Sc and WSe₂. Post metallization anneals in reducing environments (UHV, forming gas) degrade theI_ON/I_OFFby ~10³and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe₂, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe₂layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe₂Fermi level around individual Sc atoms in the WSe₂lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe₂transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe₂.

    

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4. WSe 2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing

   https://doi.org/10.1002/smll.201902770  

   Pang, Chin‐Sheng ; Chen, Chin‐Yi ; Ameen, Tarek ; Zhang, Shengjiao ; Ilatikhameneh, Hesameddin ; Rahman, Rajib ; Klimeck, Gerhard ; Chen, Zhihong ( August 2019 , Small)

   In this paper, electrostatically configurable 2D tungsten diselenide (WSe₂) electronic devices are demonstrated. Utilizing a novel triple‐gate design, a WSe₂device is able to operate as a tunneling field‐effect transistor (TFET), a metal–oxide–semiconductor field‐effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band‐to‐band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self‐consistent full‐band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub‐60 mV dec⁻¹SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low‐power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.

    

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5. High‐Performance Zinc Tin Oxide TFTs with Active Layers Deposited by Atomic Layer Deposition

   https://doi.org/10.1002/aelm.202000195  

   Allemang, Christopher R. ; Cho, Tae H. ; Trejo, Orlando ; Ravan, Shantam ; Rodríguez, Robin E. ; Dasgupta, Neil P. ; Peterson, Rebecca L. ( June 2020 , Advanced Electronic Materials)

   New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm²V⁻¹s⁻¹, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm²V^–1s^–1and a subthreshold slope of 0.29 V dec^–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐kgate insulator (ALD Al₂O₃), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates.

    

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