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Title: Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX
Last-Level Cache (LLC) attacks typically exploit timing side channels in hardware, and thus rely heavily on timers for their operation. Many proposed defenses against such side-channel attacks capitalize on this reliance. This paper presents PRIME+ABORT, a new cache attack which bypasses these defenses by not depending on timers for its function. Instead of a timing side channel, PRIME+ABORT leverages the Intel TSX hardware widely available in both server- and consumer-grade processors. This work shows that PRIME+ABORT is not only invulnerable to important classes of defenses, it also outperforms state-of-the-art LLC PRIME+PROBE attacks in both accuracy and efficiency, having a maximum detection speed (in events per second) 3× higher than LLC PRIME+PROBE on Intel’s Skylake architecture while producing fewer false positives.  more » « less
Award ID(s):
1652925
NSF-PAR ID:
10053303
Author(s) / Creator(s):
; ;
Date Published:
Journal Name:
Usenix Security
Page Range / eLocation ID:
51-67
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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