State-of-the-art machine learning models have achieved impressive feats of narrow intelligence, but have yet to realize the computational generality, adaptability, and power
efficiency of biological brains. Thus, this work aims to improve current neural network models by leveraging the principle that the cortex consists of noisy and imprecise components in order to realize an ultra-low-power stochastic spiking neural circuit that resembles biological neuronal behavior. By utilizing probabilistic spintronics to provide true stochasticity in a compact CMOS-compatible device, an Adaptive Ring Oscillator
for as-needed discrete sampling, and a homeostasis mechanism to reduce power consumption, provide additional biological characteristics, and improve process variation resilience, this subthreshold circuit is able to generate sub-nanosecond spiking behavior with biological characteristics at 200mV, using less than 80nW, along with behavioral robustness to process variation.
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Hybrid spin-CMOS stochastic spiking neuron for high-speed emulation of In vivo neuron dynamics
The spintronic stochastic spiking neuron (S3N) developed herein realizes biologically mimetic stochastic spiking characteristics observed within in vivo cortical neurons, while operating several orders of magnitude more rapidly and exhibiting a favorable energy profile. This work leverages a novel probabilistic spintronic switching element device that provides thermally-driven and current-controlled tunable stochasticity in a compact, low-energy, and high-speed package. Simulation program with integrated circuit emphasis (SPICE) simulation results indicate that the equivalent of 1 second of in vivo neuronal spiking characteristics can be generated on the order of nanoseconds, enabling the feasibility of extremely rapid emulation of in vivo neuronal behaviors for future statistical models of cortical information processing. Their results also indicate that the S3N can generate spikes on the order of ten picoseconds while dissipating only 0.6–9.6 μW, depending on the spiking rate. Additionally, they demonstrate that an S3N can implement perceptron functionality, such as AND-gate- and OR-gate-based logic processing, and provide future extensions of the work to more advanced stochastic neuromorphic architectures.
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- Award ID(s):
- 1739635
- NSF-PAR ID:
- 10057855
- Date Published:
- Journal Name:
- IET Computers & Digital Techniques
- ISSN:
- 1751-8601
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1049/iet-cdt.2017.0145
