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Title: ReRAM-based accelerator for deep learning
Big data computing applications such as deep learning and graph analytic usually incur a large amount of data movements. Deploying such applications on conventional von Neumann architecture that separates the processing units and memory components likely leads to performance bottleneck due to the limited memory bandwidth. A common approach is to develop architecture and memory co-design methodologies to overcome the challenge. Our research follows the same strategy by leveraging resistive memory (ReRAM) to further enhance the performance and energy efficiency. Specifically, we employ the general principles behind processing-in-memory to design efficient ReRAM based accelerators that support both testing and training operations. Related circuit and architecture optimization will be discussed too.  more » « less
Award ID(s):
1725456
PAR ID:
10063498
Author(s) / Creator(s):
; ; ; ; ;
Date Published:
Journal Name:
Design, Automation and Test in Europe Conference & Exhibition (DATE)
Page Range / eLocation ID:
815 to 820
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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