Industry trends are moving toward increasing use of chiplets as a replacement for monolithic fabrication in many modern chips. Each chiplet is a separately-produced silicon die, and a system-on-chip (SoC) is created by packaging the chiplets together on a silicon interposer or bridge. Chiplets enable IP reuse, heterogeneousintegration, and better ability to leverage cost-appropriate process nodes. Yet, creating systems from separately produced components also brings security risks to consider, such as the possibility of die swapping, or susceptibility to interposer probing or tampering. In a zero-trust security posture, a chiplet should not blindly assume it is operating in a friendly environment.In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure unique variations in the propagation delays of incoming signals as part of an integrity check. We prototype our design on Xilinx Ultrascale+ FPGAs, which are constructed as multi-die systems on a silicon interposer, and which also emulate the general features of other industrial chiplet interfaces. We perform experiments on, and compare data from, dozens of Ultrascale+ FPGAs by making use of Amazon’s Elastic Compute Cloud (EC2) F1 instances as a testing platform. The PUF cells are shown to reject clock and temperature variation as common mode, and each cell produces approximately 5 ps of unique delay variation. For a design with 144 PUF cells, we measure the mean within-class and between-class distances to be 68.3 ps and 847.7 ps, respectively. The smallest between-class distance of 686.0 ps exceeds the largest within-class distance of 124.0 ps by more than 5x under nominal conditions, and the PUF is shown to be resilient to environmental changes. Our findings indicate the PUF can be used for authentication, and is potentially sensitive enough to detect picosecond-scale timing changes due to tampering.
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Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions
To enable next-generation distributed and connected computing systems, we must address the context-aware chip authentication challenge. An important remaining gap in the design of these systems is the enabling of multi-personality authentication to support applications or schemes requiring a single device to own manifold legitimate identities. In this work, we propose a Multi-identity Physical Unclonable Function (Mi-PUF) assisted weighted group decision making scheme. The Mi-PUF approach enables individual devices to be authenticated and associated with multiple identities in order to hold different number of ballots. Hence, devices with higher impact in a decision making network will have more weight than the less influential ones. Besides the introduction of the scheme, the design and FPGA implementation details of the Mi-PUF are explored and presented.
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- Award ID(s):
- 1745808
- NSF-PAR ID:
- 10065467
- Date Published:
- Journal Name:
- 28th International Conference on Field Programmable Logic and Applications (FPL)
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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