Fast electrochemical imaging enables the dynamic study of electroactive molecule diffusion in neurotransmitter release from single cells and dopamine mapping in brain slices. In this paper, we discuss the design of an electrochemical imaging sensor using a monolithic CMOS sensor array and a multifunctional data acquisition system. Using post-CMOS fabrication, the CMOS sensor integrates 1024 on-chip electrodes on the surface and contains 1024 low-noise amplifiers to simultaneous process parallel electrochemical recordings. Each electrochemical electrode and amplifier are optimized to operate at 10.38 kHz sampling rate. To support the operation of the high-throughput CMOS device, a multifunctional data acquisition device is developed to provide the required speed and accuracy. The high analog data rate of 10.63 MHz from all 1024 amplifiers is redundantly sampled by the custom-designed data acquisition system which can process up to 73.6 MHz with up to ~400 Mbytes/s data rate to a computer using USB 3.0 interface. To contain the liquid above the electrochemical sensors and prevent electronic and wire damage, we packaged the monolithic sensor using a 3D-printed well. Using the presented device, 32 pixel × 32 pixel electrochemical imaging of dopamine diffusion is successfully demonstrated at over 10,000 frames per second, the fastest reported to date.
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A Half-Shared Transimpedance Amplifier Architecture for High-throughput CMOS Bioelectronics
A common problem in single-cell measurement is the low-throughput nature of measurements. Monolithic CMOS microsystems have enabled many parallel measurements to take place simultaneously to increase throughput due to the integration of electrodes and amplifiers into a single chip. This paper explores a CMOS chip containing an array of 1024 parallel transimpedance amplifiers that takes advantage of a “half-shared” operational amplifier architecture. This architecture splits a traditional 5-transistor operational amplifier into two, the inverting half and the non-inverting half. Splitting an amplifier into two allows for the non-inverting half to be “shared” with several inverting halves, reducing the die area required for each individual amplifier. This allows for an increased number of amplifiers to be embedded into the same chip; in this case, 32 amplifiers are able to fit in the same space as 17 traditional 5-transistor operational amplifiers. The amplifiers exhibit low mismatch of 1.65 mV across the entire 1024 amplifier array, as well as high linearity in transimpedance gain. The technique will enable larger arrays to be created in future designs to allow electrophysiologists, among others, access to even higher-throughput measurement tools.
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- Award ID(s):
- 1745364
- NSF-PAR ID:
- 10087751
- Date Published:
- Journal Name:
- 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)
- Page Range / eLocation ID:
- 1 to 4
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Abstract We present a new, robust three dimensional microfabrication method for highly parallel microfluidics, to improve the throughput of on-chip material synthesis by allowing parallel and simultaneous operation of many replicate devices on a single chip. Recently, parallelized microfluidic chips fabricated in Silicon and glass have been developed to increase the throughput of microfluidic materials synthesis to an industrially relevant scale. These parallelized microfluidic chips require large arrays (>10,000) of Through Silicon Vias (TSVs) to deliver fluid from delivery channels to the parallelized devices. Ideally, these TSVs should have a small footprint to allow a high density of features to be packed into a single chip, have channels on both sides of the wafer, and at the same time minimize debris generation and wafer warping to enable permanent bonding of the device to glass. Because of these requirements and challenges, previous approaches cannot be easily applied to produce three dimensional microfluidic chips with a large array of TSVs. To address these issues, in this paper we report a fabrication strategy for the robust fabrication of three-dimensional Silicon microfluidic chips consisting of a dense array of TSVs, designed specifically for highly parallelized microfluidics. In particular, we have developed a two-layer TSV design that allows small diameter vias (
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Ultra-fast & low-power superconductor single-flux-quantum (SFQ)-based CNN systolic accelerators are built to enhance the CNN inference throughput. However, shift-register (SHIFT)-based scratchpad memory (SPM) arrays prevent a SFQ CNN accelerator from exceeding 40% of its peak throughput, due to the lack of random access capability. This paper first documents our study of a variety of cryogenic memory technologies, including Vortex Transition Memory (VTM), Josephson-CMOS SRAM, MRAM, and Superconducting Nanowire Memory, during which we found that none of the aforementioned technologies made a SFQ CNN accelerator achieve high throughput, small area, and low power simultaneously. Second, we present a heterogeneous SPM architecture, SMART, composed of SHIFT arrays and a random access array to improve the inference throughput of a SFQ CNN systolic accelerator. Third, we propose a fast, low-power and dense pipelined random access CMOS-SFQ array by building SFQ passive-transmission-line-based H-Trees that connect CMOS sub-banks. Finally, we create an ILP-based compiler to deploy CNN models on SMART. Experimental results show that, with the same chip area overhead, compared to the latest SHIFT-based SFQ CNN accelerator, SMART improves the inference throughput by 3.9 × (2.2 ×), and reduces the inference energy by 86% (71%) when inferring a single image (a batch of images).more » « less
- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/BIOCAS.2018.8584792
