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1. Doubly 1-Bit Quantized Massive MIMO

   https://doi.org/10.1109/IEEECONF59524.2023.10476782  

   Atzeni, Italo; Tölli, Antti; Nguyen, Duy_H N; Swindlehurst, A Lee (October 2023, IEEE)

   Enabling communications in the (sub-)THz band will call for massive multiple-input multiple-output (MIMO) arrays at either the transmit- or receive-side, or at both. To scale down the complexity and power consumption when operating across massive frequency and antenna dimensions, a sacrifice in the resolution of the digital-to-analog/analog-to-digital converters (DACs/ADCs) will be inevitable. In this paper, we analyze the extreme scenario where both the transmit- and receive-side are equipped with fully digital massive MIMO arrays and 1-bit DACs/ADCs, which leads to a system with minimum radio-frequency complexity, cost, and power consumption. Building upon the Bussgang decomposition, we derive a tractable approximation of the mean squared error (MSE) between the transmitted data symbols and their soft estimates. Numerical results show that, despite its simplicity, a doubly 1-bit quantized massive MIMO system with very large antenna arrays can deliver an impressive performance in terms of MSE and symbol error rate. 

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2. One-Bit Massive MIMO Precoding for Frequency-Selective Fading Channels

   https://doi.org/10.1109/SSP53291.2023.10207951  

   Nguyen, Ly V.; Liu, Lu; Linh-Trung, Nguyen; Swindlehurst, A. Lee (July 2023, Proceedings of the 2023 IEEE Statistical Signal Processing Workshop (SSP))

   One-bit digital-to-analog converters (DACs) are a practical and promising solution for reducing cost and power consumption in massive multiple-input multiple-output (MIMO) systems. However, the one-bit precoding problem is NP-hard and even more challenging in frequency-selective fading channels compared to the flat-fading scenario. While block-wise processing (BWP) can effectively address the inter-symbol-interference (ISI) in frequency-selective fading channels, its computational complexity and processing delay can be too high for practical implementation. An alternative solution to alleviate the processing complexity and delay issues is symbol-wise processing (SWP) which sequentially designs the transmit signals. However, existing SWP work leaves unwanted interference for later signal designs. In this paper, we propose an SWP approach which can efficiently address the ISI even at the symbol rate. The idea is to design the transmit signal to not only be beneficial for its time slot, but also to provide constructive interference for subsequent symbols. We develop two active ISI processing methods that significantly outperform a conventional approach, one of which that even outperforms the BWP approach at low SNR. 

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3. Discrete Phase Shift Design for Practical Large Intelligent Surface Communication

   https://doi.org/10.1109/PACRIM47961.2019.8985103  

   Xu, Jindan; Xu, Wei; Swindlehurst, A. Lee (August 2019, Proc. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM))

   In this paper, we investigate a downlink channel of a large intelligent surface (LIS) communication system. The LIS is equipped with B-bit discrete phase shifts while base station (BS) exploits low-resolution digital-to-analog converters (DACs). Without the knowledge of channel state information (CSI) related to the LIS, we propose a practical phase shift design method, whose computational complexity increases by 2 B independent of the number of reflecting elements N. A tight lower bound for the asymptotic rate of the user is obtained in closed form. As N increases, we observe that the asymptotic rate becomes saturated because both the received signal power and the DAC quantization noise increase. Compared to the optimal continuous phase shift design with perfect CSI, our proposed method asymptotically approaches the ideal benchmark performance for moderate to high values of B. The derived results and observations are verified by simulation results. 

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4. Exploitation of Symmetrical Non-Convexity for Symbol-Level DFRC Signal Design

   https://doi.org/10.1109/ICC51166.2024.10622712  

   Nguyen, Ly V; Liu, Rang; Swindlehurst, A Lee (June 2024, IEEE)

   Constructive interference exploited by symbol-level (SL) signal processing is a promising solution for addressing the inherent interference problem in dual-functional radar-communication (DFRC) signal designs. This paper considers an SL-DFRC signal design problem which maximizes the radar performance under communication performance constraints. We exploit the symmetrical non-convexity property of the communication-independent radar sensing metric to develop low- complexity yet efficient algorithms. We first propose a radar-to- DFRC (R2DFRC) algorithm that relies on the non-convexity of the radar sensing metric to find a set of radar-only solutions. Based on these solutions, we further exploit the symmetrical property of the radar sensing metric to efficiently design the DFRC signal. Since the radar sensing metric is independent of the communication channel and data symbols, the set of radar-only solutions can be constructed offline, therefore reducing the computational complexity. We then develop an accelerated R2DFRC algorithm that further reduces the complexity. Finally, we demonstrate the superiority of the proposed algorithms compared to existing methods in terms of both radar sensing and communication performance as well as computational complexity. 

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5. Leveraging neuro-inspired AI accelerator for high-speed computing in 6G networks

   https://doi.org/10.3389/fncom.2024.1345644  

   Lin, Chunxiao; Azmine, Muhammad Farhan; Liang, Yibin; Yi, Yang (February 2024, Frontiers in Computational Neuroscience)

   The field of wireless communication is currently being pushed to new boundaries with the emergence of 6G technology. This advanced technology requires substantially increased data rates and processing speeds while simultaneously requiring energy-efficient solutions for real-world practicality. In this work, we apply a neuroscience-inspired machine learning model called echo state network (ESN) to the critical task of symbol detection in massive MIMO-OFDM systems, a key technology for 6G networks. Our work encompasses the design of a hardware-accelerated reservoir neuron architecture to speed up the ESN-based symbol detector. The design is then validated through a proof of concept on the Xilinx Virtex-7 FPGA board in real-world scenarios. The experiment results show the great performance and scalability of our symbol detector design across a range of MIMO configurations, compared with traditional MIMO symbol detection methods like linear minimum mean square error. Our findings also confirm the performance and feasibility of our entire system, reflected in low bit error rates, low resource utilization, and high throughput. 

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