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1. Security Oriented Analog Circuit Design Using Satisfiability Modulo Theory Based Search Space Exploration

   Rao, Vaibhav. ; Savidis, Ioannis ( March 2018 , Government Microcircuit Applications & Critical Technology Conference)

   A technique to enhance the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration is described. The analog satisfiability (aSAT) technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The aSAT methodology is applied to parameter biasing obfuscation, where the width and length of a transistor are obfuscated to mask circuit properties. The proposed methodology was used in the design of a differential amplifier and an operational amplifier, where the widths and lengths determined through aSAT analysis were shown to meet the target circuit specifications. For the operational amplifier, transistor dimensions determined through aSAT analysis for a set of performance constraints were characterized and were found to meet the performance targets, however, there was a 7 MHz reduction in the gain bandwidth product. The simulated results indicate that the developed design methodology achieves a fast and accurate determination of transistor sizes for target specifications. 

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2. Security Vulnerabilities of Obfuscated Analog Circuits

   https://doi.org/10.1109/ISCAS45731.2020.9180781  

   Rao, Vaibhav Venugopal ; Juretus, Kyle ; Savidis, Ioannis ( October 2020 , Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS))

   null (Ed.)

   Vulnerabilities of key based analog obfuscation methodologies that modify the transistor dimensions of a circuit are evaluated. Two attack vectors on a common source amplifier, differential amplifier, operational amplifier, and voltage controlled oscillator are developed. The first attack exploits the lack of possible key combinations permitted around the correct key, which is a result of requiring a unique key to lock the circuit. An average of 5 possible key combinations were returned in an average of 5.47 seconds when executing the key spacing attack. The second attack vector utilizes the monotonic relationship between the sizing of the transistors and the functional response of the circuit to determine the correct key. The average time to execute the attack, while assuming process, voltage, and temperature (PVT) variation of 10%, was 1.18 seconds. Both equal key spacing and non-monotonic key dependencies are discussed as ways to mitigate the threats to future analog obfuscation techniques. 

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3. Design Automation of CMOS Op-Amps Using Statistical Geometric Programming

   Roychowdhury, Sangjukta ; Bhardwaj, Sumit ; Kitchen, Jennifer ( April 2022 , Proceedings IEEE International Symposium on Circuits and Systems)

   This work proposes a novel design automation (DA) technique that uses a multifaceted approach combining Multivariate Regression with Geometric Programming (GP) to design analog circuits. Previous DA methods employing GP have typically used analytical derivations of the various design equations representing an analog circuit. The proposed DA method eliminates the need for analytical derivations by using simulation data and multivariate regression to generate statistical models combined with GP to solve these statistical expressions with respect to optimum circuit design parameters. This presented statistical GP method has been applied to successfully design a five-transistor two-stage operational amplifier and a folded cascode amplifier in a TSMC 65nm CMOS technology. The presented statistical GP DA results are comparable to the design results obtained from both analytical GP 

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4. CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing

   https://doi.org/10.1145/3380446.3430633  

   Wu, Zhengfeng ; Savidis, Ioannis ( November 2020 , Proceedings of the ACM/IEEE Workshop on Machine Learning for Computer Aided Design (MLCAD))

   null (Ed.)

   A novel simulation-based framework that applies classification with adaptive labeling thresholds (CALT) is developed that auto-generates the component sizes of an analog integrated circuit. Classifiers are applied to predict whether the target specifications are satisfied. To address the lack of data points with positive labels due to the large dimensionality of the parameter space, the labeling threshold is adaptively set to a certain percentile of the distribution of a given circuit performance metric in the dataset. Random forest classifiers are executed for surrogate prediction modeling that provide a ranking of the design parameters. For each iteration of the simulation loop, optimization is utilized to determine new query points. CALT is applied to the design of a low noise amplifier (LNA) in a 65 nm technology. Qualified design solutions are generated for two sets of specifications with an average execution of 4 and 17 iterations of the optimization loop, which require an average of 1287 and 2190 simulation samples, and an average execution time of 5.4 hours and 23.2 hours, respectively. CALT is a specification-driven design framework to automate the sizing of the components (transistors, capacitors, inductors, etc.) of an analog circuit. CALT generates interpretable models and achieves high sample efficiency without requiring the use of prior circuit models. 

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5. A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

   https://doi.org/10.3390/electronics10050590  

   Tasneem, Nishat Tarannum ; Mahbub, Ifana ( March 2021 , Electronics)

   This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system. 

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