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1. Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory

   https://doi.org/10.1109/APCCAS.2018.8605710  

   Rao, Vaibhav Venugopal; Savidis, Ioannis (October 2018, IEEE International Asia Pacific Conference on Circuits and Systems)

   In this paper, an approach is described for enhancing the security of analog circuits using Satisfiability Modulo theory (SMT) based design space exploration. The technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The analog satisfiability (aSAT) methodology is applied to parameter biasing obfuscation, where the width of a transistor is obfuscated to mask circuit properties, while also limiting the number of keys that produce the target performance requirements. The proposed methodology is used in the design of a differential amplifier and a two stage amplifier. The widths determined through aSAT analysis are shown to meet the gain, phase margin, and power consumption requirements for both a differential amplifier and a two-stage amplifier. However, a 7 MHz offset in the gain-bandwidth of the two-stage amplifier is observed from the target value of 30 MHz. The total gain of the two stage amplifier is masked with a 24 bit encryption key that results in a probability of 5.96x10-08 to determine the correct key. The simulated results indicate that the proposed analog design methodology quickly and accurately determines transistor sizes for target specifications, while also accounting for obfuscation of analog circuit parameters. 

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2. Design Automation of CMOS Op-Amps Using Statistical Geometric Programming

   Roychowdhury, Sangjukta; Bhardwaj, Sumit; Kitchen, Jennifer (April 2022, Proceedings IEEE International Symposium on Circuits and Systems)

   This work proposes a novel design automation (DA) technique that uses a multifaceted approach combining Multivariate Regression with Geometric Programming (GP) to design analog circuits. Previous DA methods employing GP have typically used analytical derivations of the various design equations representing an analog circuit. The proposed DA method eliminates the need for analytical derivations by using simulation data and multivariate regression to generate statistical models combined with GP to solve these statistical expressions with respect to optimum circuit design parameters. This presented statistical GP method has been applied to successfully design a five-transistor two-stage operational amplifier and a folded cascode amplifier in a TSMC 65nm CMOS technology. The presented statistical GP DA results are comparable to the design results obtained from both analytical GP 

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3. CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing

   https://doi.org/10.1145/3380446.3430633  

   Wu, Zhengfeng; Savidis, Ioannis (November 2020, Proceedings of the ACM/IEEE Workshop on Machine Learning for Computer Aided Design (MLCAD))

   null (Ed.)

   A novel simulation-based framework that applies classification with adaptive labeling thresholds (CALT) is developed that auto-generates the component sizes of an analog integrated circuit. Classifiers are applied to predict whether the target specifications are satisfied. To address the lack of data points with positive labels due to the large dimensionality of the parameter space, the labeling threshold is adaptively set to a certain percentile of the distribution of a given circuit performance metric in the dataset. Random forest classifiers are executed for surrogate prediction modeling that provide a ranking of the design parameters. For each iteration of the simulation loop, optimization is utilized to determine new query points. CALT is applied to the design of a low noise amplifier (LNA) in a 65 nm technology. Qualified design solutions are generated for two sets of specifications with an average execution of 4 and 17 iterations of the optimization loop, which require an average of 1287 and 2190 simulation samples, and an average execution time of 5.4 hours and 23.2 hours, respectively. CALT is a specification-driven design framework to automate the sizing of the components (transistors, capacitors, inductors, etc.) of an analog circuit. CALT generates interpretable models and achieves high sample efficiency without requiring the use of prior circuit models. 

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4. Security Vulnerabilities of Obfuscated Analog Circuits

   https://doi.org/10.1109/ISCAS45731.2020.9180781  

   Rao, Vaibhav Venugopal; Juretus, Kyle; Savidis, Ioannis (October 2020, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS))

   null (Ed.)

   Vulnerabilities of key based analog obfuscation methodologies that modify the transistor dimensions of a circuit are evaluated. Two attack vectors on a common source amplifier, differential amplifier, operational amplifier, and voltage controlled oscillator are developed. The first attack exploits the lack of possible key combinations permitted around the correct key, which is a result of requiring a unique key to lock the circuit. An average of 5 possible key combinations were returned in an average of 5.47 seconds when executing the key spacing attack. The second attack vector utilizes the monotonic relationship between the sizing of the transistors and the functional response of the circuit to determine the correct key. The average time to execute the attack, while assuming process, voltage, and temperature (PVT) variation of 10%, was 1.18 seconds. Both equal key spacing and non-monotonic key dependencies are discussed as ways to mitigate the threats to future analog obfuscation techniques. 

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5. Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

   https://doi.org/10.23919/DATE48585.2020.9116330  

   Liu, Mingjie; Zhu, Keren; Gu, Jiaqi; Shen, Linxiao; Tang, Xiyuan; Sun, Nan; Pan, David Z. (March 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE))

   Despite tremendous efforts in analog layout automation, little adoption has been demonstrated in practical design flows. Traditional analog layout synthesis tools use various heuristic constraints to prune the design space to ensure post layout performance. However, these approaches provide limited guarantee and poor generalizability due to a lack of model mapping layout properties to circuit performance. In this paper, we attempt to shorten the gap in post layout performance modeling for analog circuits with a quantitative statistical approach. We leverage a state-of-the-art automatic analog layout tool and industry-level simulator to generate labeled training data in an automated manner. We propose a 3D convolutional neural network (CNN) model to predict the relative placement quality using well-crafted placement features. To achieve data-efficiency for practical usage, we further propose a transfer learning scheme that greatly reduces the amount of data needed. Our model would enable early pruning and efficient design explorations for practical layout design flows. Experimental results demonstrate the effectiveness and generalizability of our method across different operational transconductance amplifier (OTA) designs. 

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