Gopal, Srinivasan, Agarwal, Pawan, Baylon, Joe, Renaud, Luke, Ali, Sheikh Nijam, Pande, Partha Pratim, and Heo, Deukhyoun. A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS. Retrieved from https://par.nsf.gov/biblio/10094499. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8.3 Web. doi:10.1109/JETCAS.2018.2852624.

Gopal, Srinivasan, Agarwal, Pawan, Baylon, Joe, Renaud, Luke, Ali, Sheikh Nijam, Pande, Partha Pratim, & Heo, Deukhyoun. A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8 (3). Retrieved from https://par.nsf.gov/biblio/10094499. https://doi.org/10.1109/JETCAS.2018.2852624

Gopal, Srinivasan, Agarwal, Pawan, Baylon, Joe, Renaud, Luke, Ali, Sheikh Nijam, Pande, Partha Pratim, and Heo, Deukhyoun. "A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS". IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3). Country unknown/Code not available. https://doi.org/10.1109/JETCAS.2018.2852624. https://par.nsf.gov/biblio/10094499.

@article{osti_10094499,
place = {Country unknown/Code not available}, title = {A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS}, url = {https://par.nsf.gov/biblio/10094499}, DOI = {10.1109/JETCAS.2018.2852624}, abstractNote = {}, journal = {IEEE Journal on Emerging and Selected Topics in Circuits and Systems}, volume = {8}, number = {3}, author = {Gopal, Srinivasan and Agarwal, Pawan and Baylon, Joe and Renaud, Luke and Ali, Sheikh Nijam and Pande, Partha Pratim and Heo, Deukhyoun}, }