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Active control of interference is necessary with increased cell density, more complicated environmental reflections, and coexistence of multiple networks for next-generation wireless communications. The existing radio receiver architectures for spatial interference cancellation (SpICa) are limited by the spatial nulls created by a phased-antenna array (PAA) and cannot cover wide modulated bandwidths (BWs). We propose a discrete-time-delay-compensating technique for canceling spatial interferences with wide modulated BWs to reduce the dynamic range requirement for the data converter. Integral to the proposed circuit is a switched-capacitor-based multiply-and-accumulate processor that incorporates a reconfigurable phase interpolator and time interleaver for precise digitally tunable delays and multiplication of the input signal to an orthogonal matrix. The digital time interleaver enables 5-ps resolution with a reconfigurable range up to 15 ns. The measured results demonstrate greater than 35-dB SpICa over 80-MHz modulated BWs in the 65-nm CMOS with 52 mW of power consumption. 

To improve the power delivery in System-on-Chips (SoCs), this paper proposes a single-input-multi-output (SIMO) hybrid converter to obtain fast response time, low cross-regulation, and 87% peak efficiency by using a multi-output hybrid power stage and dual-switching-frequency technique. The multiple-output hybrid power stage improves the conversion efficiency without sacrificing the output voltage range, and the dual-switching-frequency technique enhances the response time and cross-regulation performance. The proposed SIMO hybrid converter achieves 87.5% peak efficiency with an output voltage range from 0.4V to 1.6V for all outputs and a total maximum load current of 450mAAdditionally, it achieves less than 0.01mA/mV cross-regulation and less than 20mV overshoot at full-load step transient response. 

This paper presents a new continually-stepped variable gain low-noise-amplifier (CSVG-LNA) for millimeter-wave (mm-wave) 5G communications. The proposed variable-gain functionality in a two-stage LNA is achieved by incorporating a tunable-transformer at the 2nd-stage. The tunability in coupling-coefficient of the transformer allows to change the output matching of the LNA in a continuous fashion thus enabling a design of CSVG-LNA. The proposed CSVG-LNA alleviates high power consumption and large noise-figure (NF) variation problems in traditional approaches. To validate the proposed idea, we fabricated a CSVG-LNA in 65-nm CMOS process. The CSVG-LNA achieves measured 6.2dB of gain-tunability range while producing 18.2dB of peak S21 and <;4.1dB of NF 28GHz. Further, the NF variation is only ~0.2dB across the entire 6.2dB gain-tuning range. The 3dB bandwidth of CSVG-LNA is about 12GHz (22-34GHz) while it consumes only 9.8mW of dc power. The CSVG-LNA occupies a compact core area of 0.2mm2. The proposed CSVG-LNA achieves 1.5X improvement in FoM in comparison to state-of-the-arts mm-wave variable-gain CMOS LNAs. 

This paper presents a dual-band RF rectifying circuit for wireless power transmission at 1.17 GHz and 2.4 GHz. A dual-band harmonic-tuned inverse-class F/class-F mode power amplifier using a 10 W GaN device has been utilized to implement the proposed rectifier with an on-board coupler and phase shifter. The matching circuit is precisely designed so that the circuit operates in inverse class F and class F mode in the lower and upper frequency bands using dual-band harmonic tuning, respectively. Measurement results show that the rectifier circuit has 78% and 76% efficiencies at 1.17 GHz and 2.4 GHz frequency bands, respectively. To the best of the authors' knowledge, this rectifier is the first demonstration of a dual-band harmonic-tuned synchronous rectifier using a GaN HEMT device with an integrated coupler and phase-shifter for a watt-level RF input power. 

To mitigate large voltage droop caused by sub-ns dynamic current transitions in system on chips (SoCs), this paper proposes a fully integrated analog-assisted inverter-based digital low dropout regulator (LDO) to obtain a fast response time with 160mV droop at 25mA/100ps featuring 99.4% current efficiency, and 16mV DC load regulation in sub-1V operating range by using a dynamic-step quantizer and a trip-point controller. The proposed quantizer is implemented with an inverter-based flash ADC to achieve high speed without consuming large power while the trip-point controller corrects the DC error of the inverter-based ADC. Besides, the assistant analog LDO is employed to provide fine-grain regulation and remove ripple from the output voltage.