More Like this

1. 29.8 SHARC: Self-Healing Analog with RRAM and CNFETs

   https://doi.org/10.1109/ISSCC.2019.8662377  

   Amer, Aya G.; Ho, Rebecca; Hills, Gage; Chandrakasan, Anantha P.; Shulaker, Max M. (February 2019, SHARC: Self-Healing Analog with RRAM and CNFETs)

   Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology for energy-efficient electronics (Fig. 1). Despite this promise, CNTs are subject to substantial inherent imperfections; every ensemble of CNTs includes some percentage of metallic CNTs (m-CNTs). m-CNTs result in conductive shorts between CNFET source and drain, resulting in excessive leakage and degraded (potentially incorrect) circuit functionality (Fig. 1). Several techniques have been developed to remove the majority of m-CNTs (no technique today removes 100% of m-CNTs). While these techniques enabled the first digital CNFET circuits, it is still not possible to realize large-scale CNFET analog or mixed-signal CNFET circuits due to m-CNTs. As shown in Fig. 1, while a digital logic gate can still function correctly in the presence of a small fraction of m-CNTs (but with degraded resilience to noise) [1], a single m-CNT in an analog circuit can result in catastrophic failure (e.g., degrading amplifier gain resulting in functional failure of circuit blocks such as ADCs and DACs)1. This paper presents a circuit design technique, Self-Healing Analog with RRAM and CNFETs (SHARC), that leverages the programmability of non-volatile resistive RAM (RRAM) to automatically “self-heal” analog circuits in the presence of m-CNTs. Using SHARC, we experimentally demonstrate analog CNFET circuits robust to m-CNTs as well as the first mixed-signals CNFET subsystem (4-bit DAC and SAR ADC; these are the largest reported complementary (CMOS) CNFET circuit demonstrations to-date). 

   more » « less
2. An offset calibration scheme for on-chip thermal profiling with differential temperature sensors

   https://doi.org/10.1007/s10470-024-02285-w  

   Yan, Mengting; Onabajo, Marvin (July 2024, Analog Integrated Circuits and Signal Processing)

   This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage offset due to device mismatches and on-chip temperature gradients. The calibration circuits were designed in a standard 65 nm CMOS process for simulation. Results indicate that an input-referred offset with a mean of 0.2 μV can be achieved after calibration, through which the standard deviation is greatly reduced from σ = 880.3 μV to σ = 5086 μV. Furthermore, the proposed analog offset calibration scheme has negligible impact on the sensitivity of the complete temperature sensor circuit, as shown by Monte Carlo and process-temperature corner simulation results. 

   more » « less
3. Heterogeneous Integration of Atomically Thin Semiconductors for Non‐von Neumann CMOS

   https://doi.org/10.1002/smll.202202590  

   Pendurthi, Rahul; Jayachandran, Darsith; Kozhakhmetov, Azimkhan; Trainor, Nicholas; Robinson, Joshua A.; Redwing, Joan M.; Das, Saptarshi (July 2022, Small)

   Abstract Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high‐performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n‐type TMDs such as MoS₂and WS₂grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p‐type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n‐type MoS₂and p‐type vanadium doped WSe₂FETs with non‐volatile and analog memory storage capabilities to achieve a non–von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n‐type and p‐type FETs, which is critical for any IC development. Inverters and a simplified 2‐input‐1‐output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non–von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials. 

   more » « less
4. Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications

   https://doi.org/10.3390/math8050829  

   Chen, Ethan; Chen, Vanessa (May 2020, Mathematics)

   While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications. 

   more » « less
5. Si0.97Ge0.03 microelectronic thermoelectric generators with high power and voltage densities

   https://doi.org/10.1038/s41467-020-18122-3  

   Dhawan, Ruchika; Madusanka, Prabuddha; Hu, Gangyi; Debord, Jeff; Tran, Toan; Maggio, Kenneth; Edwards, Hal; Lee, Mark (August 2020, Nature Communications)

   Abstract Microelectronic thermoelectric generators are one potential solution to energizing energy autonomous electronics, such as internet-of-things sensors, that must carry their own power source. However, thermoelectric generators with the mm²footprint area necessary for on-chip integration made from high thermoelectric figure-of-merit materials have been unable to produce the voltage and power levels required to run Si electronics using common temperature differences. We present microelectronic thermoelectric generators using Si_0.97Ge_0.03, made by standard Si processing, with high voltage and power generation densities that are comparable to or better than generators using high figure-of-merit materials. These Si-based thermoelectric generators have <1 mm²areas and can energize off-the-shelf sensor integrated circuits using temperature differences ≤25 K near room temperature. These generators can be directly integrated with Si circuits and scaled up in area to generate voltages and powers competitive with existing thermoelectric technologies, but in what should be a far more cost-effective manner. 

   more » « less