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1. A Low-Power Differential Temperature Sensor with Chopped Cascode Transistors and Switched-Capacitor Integration

   https://doi.org/10.3390/electronics14122381  

   Yang, Junyi; Gourousis, Thomas; Yan, Mengting; Ding, Ruyi; Mittal, Ankit; Zhang, Milin; Restuccia, Francesco; Shrivastava, Aatmesh; Fei, Yunsi; Onabajo, Marvin (June 2025, Electronics)

   Embedded differential temperature sensors can be utilized to monitor the power consumption of circuits, taking advantage of the inherent on-chip electrothermal coupling. Potential applications range from hardware security to linearity, gain/bandwidth calibration, defect-oriented testing, and compensation for circuit aging effects. This paper introduces the use of on-chip differential temperature sensors as part of a wireless Internet of Things system. A new low-power differential temperature sensor circuit with chopped cascode transistors and switched-capacitor integration is described. This design approach leverages chopper stabilization in combination with a switched-capacitor integrator that acts as a low-pass filter such that the circuit provides offset and low-frequency noise mitigation. Simulation results of the proposed differential temperature sensor in a 65 nm complementary metal-oxide-semiconductor (CMOS) process show a sensitivity of 33.18V/°C within a linear range of ±36.5m°C and an integrated output noise of 0.862mVrms (from 1 to 441.7 Hz) with an overall power consumption of 0.187mW. Considering a figure of merit that involves sensitivity, linear range, noise, and power, the new temperature sensor topology demonstrates a significant improvement compared to state-of-the-art differential temperature sensors for on-chip monitoring of power dissipation. 

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2. Massive MIMO Channel Estimation with 1-Bit Spatial Sigma-delta ADCs

   https://doi.org/10.1109/ICASSP.2019.8682842  

   Rao, Shilpa; Swindlehurst, A. Lee; Pirzadeh, Hessam (May 2019, 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP))

   We consider channel estimation for an uplink massive multiple input multiple output (MIMO) system where the base station (BS) uses a first-order spatial Sigma-Delta (Σ△) analog-to-digital converter (ADC) array. The Σ△ array consists of closely spaced sensors which oversample the received signal and provide a coarsely quantized (1-bit) output. We develop a linear minimum mean squared error (LMMSE) estimator based on the Bussgang decomposition that reformulates the nonlinear quantizer model using an equivalent linear model plus quantization noise. The performance of the proposed Σ△ LMMSE estimator is compared via simulation to channel estimation using standard 1-bit quantization and also infinite resolution ADCs. 

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3. RF-PUF: IoT security enhancement through authentication of wireless nodes using in-situ machine learning

   https://doi.org/10.1109/hst.2018.8383916  

   Chatterjee, Baibhab; Das, Debayan; Sen, Shreyas (April 2018, 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST))

   Physical unclonable functions (PUF) in silicon exploit die-to-die manufacturing variations during fabrication for uniquely identifying each die. Since it is practically a hard problem to recreate exact silicon features across dies, a PUF-based authentication system is robust, secure and cost-effective, as long as bias removal and error correction are taken into account. In this work, we utilize the effects of inherent process variation on analog and radio-frequency (RF) properties of multiple wireless transmitters (Tx) in a sensor network, and detect the features at the receiver (Rx) using a deep neural network based framework. The proposed mechanism/ framework, called RF-PUF, harnesses already-existing RF communication hardware and does not require any additional PUF-generation circuitry in the Tx for practical implementation. Simulation results indicate that the RF-PUF framework can distinguish up to 10000 transmitters (with standard foundry defined variations for a 65 nm process, leading to non-idealities such as LO offset and I-Q imbalance) under varying channel conditions, with a probability of false detection <10^-3 

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4. A Low-power Reconfigurable Readout Circuit with Large DC Offset Reduction for Neural Signal Recording Applications

   https://doi.org/10.1109/MWSCAS48704.2020.9184526  

   Tasneem, Nishat; Mahbub, Ifana (August 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS))

   null (Ed.)

   This paper presents a fully reconfigurable readout circuit including a chopper-stabilized neural amplifier and a successive approximation register (SAR) analog-to-digital converter (ADC) for neural signal recording applications. Since the target neural signals - action potentials (APs) and local field potentials (LFPs) differ in the peak amplitude while occupying different frequency bandwidths, gain, and bandwidth reconfigurability would be advantageous in improving power and noise performance. The readout circuit is designed in 180 nm standard CMOS technology. It achieves the mid-band gain of 50.3 dB in the frequency band of 0.1 Hz - 250 Hz to detect the LFPs, and 63.4 dB in 267 Hz - 20.8 kHz for detecting the APs. The neural amplifier consumes a total power of 1.54 μW and 1.94 μW for LFP and AP configurations, respectively. The input-referred noises have been achieved as 0.97 μV rms (0.1 Hz - 250 Hz), and 0.44 μV rms (250 Hz - 5 kHz), leading to a noise efficiency factor (NEF) of 1.27 and 1.21, for the two configurations, respectively. It rejects the generated large DC offset up to 40 mV at the electrode-tissue interface, by implementing a DC servo loop (DSL). The offset voltage with the DSL becomes 0.23 mV, which is acceptable for the neural experiments. Enabling the impedance boosting loop, the DC input impedance is found to be within the range of 1.77 - 2.27 GΩ, introducing the reconfigurability in impedance for matching with the electrode impedance. The SAR-ADC having a varying sampling frequency ranging from 10 - 40 ksamples/s demonstrates to digitize the APs and the LFPs with the resolution from 8 - 10 bits. The entire AFE provides good compatibility to record the neural signal while lowering the large DC offset down to 0.23 mV. 

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5. An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technology

   https://doi.org/10.1145/3195970.3195989  

   Mahmoodi, M. Reza; Strukov, Dmitri (May 2018, ACM/IEEE Design Automation Conference (DAC'18))

   Vector-matrix multiplication (VMM) is a core operation in many signal and data processing algorithms. Previous work showed that analog multipliers based on nonvolatile memories have superior energy efficiency as compared to digital counterparts at low-to-medium computing precision. In this paper, we propose extremely energy efficient analog mode VMM circuit with digital input/output interface and configurable precision. Similar to some previous work, the computation is performed by gate-coupled circuit utilizing embedded floating gate (FG) memories. The main novelty of our approach is an ultra-low power sensing circuitry, which is designed based on translinear Gilbert cell in topological combination with a floating resistor and a low-gain amplifier. Additionally, the digital-to-analog input conversion is merged with VMM, while current-mode algorithmic analog-to-digital circuit is employed at the circuit backend. Such implementations of conversion and sensing allow for circuit operation entirely in a current domain, resulting in high performance and energy efficiency. For example, post-layout simulation results for 400×400 5-bit VMM circuit designed in 55 nm process with embedded NOR flash memory, show up to 400 MHz operation, 1.68 POps/J energy efficiency, and 39.45 TOps/mm2 computing throughput. Moreover, the circuit is robust against process-voltage-temperature variations, in part due to inclusion of additional FG cells that are utilized for offset compensation. 

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