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1. TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs

   https://doi.org/10.1109/ReConFig48160.2019.8994782  

   Thurlow, Corbin; Rowberry, Hayden; Wirthlin, Michael (December 2019, 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig))

   This paper presents the TURTLE fault injection platform for inserting faults into SRAM FPGAs. The TURTLE system is designed to gather significant fault injection data to test and validate radiation-induced single-event upset (SEU) mitigation techniques for FPGAs. The TURTLE is a low-cost fault injection platform that emulates upsets within the configuration memory (CRAM) of an FPGA through partial reconfiguration. This work successfully implemented the proposed architecture and performed several successful fault injection campaigns on multiple designs and SEU mitigation techniques. Results in this paper show large amounts of data collected from a fault injection campaign used to validate the PCMF SEU mitigation technique. Over 170 million injections were performed using the TURTLE for this campaign. 

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2. Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC

   https://doi.org/10.1145/3543622.3573191  

   Wilson, Andrew Elbert; Baker, Nathan; Campbell, Ethan; Sahleen, Jackson; Wirthlin, Michael (February 2023, Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays)

   FPGAs are increasingly being used in space and other harsh radiation environments. However, SRAM-based FPGAs are susceptible to radiation in these environments and experience upsets within the configuration memory (CRAM), causing design failure. The effects of CRAM upsets can be mitigated using triple-modular redundancy and configuration scrubbing. This work investigates the reliability of a soft RISC-V SoC system executing the Linux operating system mitigated by TMR and configuration scrubbing. In particular, this paper analyzes the failures of this triplicated system observed at a high-energy neutron radiation experiment. Using a bitstream fault analysis tool, the failures of this system caused by CRAM upsets are traced back to the affected FPGA resource and design logic. This fault analysis identifies the interconnect and I/O as the most vulnerable FPGA resources and the DDR controller logic as the design logic most likely to cause a failure. By identifying the FPGA resources and design logic causing failures in this TMR system, additional design enhancements are proposed to create a more reliable design for harsh radiation environments. 

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3. DMR-SCL: A Design and Verification Framework for Redundancy-Based Resilient Asynchronous Sleep Convention Logic Circuits

   https://doi.org/10.3390/electronics14050884  

   Datta, Mithun; Mazumder, Dipayan; Bodoh, Alexander C; Sakib, Ashiq A (March 2025, Electronics)

   The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to transient errors, caused by radiation rays, power jitters, electromagnetic interferences (EMIs), and/or other noise sources, primarily due to aggressive device and voltage scaling. quasi-delay-insensitive (QDI) asynchronous (clockless) circuits demonstrate inherent robustness against such transient errors, owing to their unique architecture. However, they are not completely immune. This article presents a hardened QDI Sleep Convention Logic (SCL) asynchronous architecture, which can fully recover from radiation-induced single-event effects such as single-event upset (SEU) and single-event latch-up (SEL). Multiple benchmark circuits are designed based on the proposed architecture. The simulation results indicate that the proposed designs offer substantial energy savings per operation, dissipate substantially less power during idle phases, and have lower area footprints in comparison to designs based on an existing resilient Null Convention Logic (NCL) architecture at the cost of increased latency. In addition, a formal verification framework for the proposed architecture is also presented. The performance and scalability of the proposed verification scheme are demonstrated using several multiplier benchmark circuits of varying width. 

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4. Logical quantum processor based on reconfigurable atom arrays

   https://doi.org/10.1038/s41586-023-06927-3  

   Bluvstein, Dolev; Evered, Simon J.; Geim, Alexandra A.; Li, Sophie H.; Zhou, Hengyun; Manovitz, Tom; Ebadi, Sepehr; Cain, Madelyn; Kalinowski, Marcin; Hangleiter, Dominik; et al (December 2023, Nature)

   Abstract Suppressing errors is the central challenge for useful quantum computing¹, requiring quantum error correction (QEC)^2–6for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy^2–4, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays⁷, our system combines high two-qubit gate fidelities⁸, arbitrary connectivity^7,9, as well as fully programmable single-qubit rotations and mid-circuit readout^10–15. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code⁶distance fromd = 3 tod = 7, preparation of colour-code qubits with break-even fidelities⁵, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks^16,17, we realize computationally complex sampling circuits¹⁸with up to 48 logical qubits entangled with hypercube connectivity¹⁹with 228 logical two-qubit gates and 48 logical CCZ gates²⁰. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling^21,22. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors. 

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5. Measurement of the multineutron ${\overline{\nu }}_{\mu }$ charged current differential cross section at low available energy on hydrocarbon

   https://doi.org/10.1103/PhysRevD.108.112010  

   Olivier, A; Cai, T; Akhter, S; Ahmad_Dar, Z; Ansari, V; Ascencio, M V; Sajjad_Athar, M; Bashyal, A; Bercellie, A; Betancourt, M; et al (December 2023, Physical Review D)

   Neutron production in antineutrino interactions can lead to bias in energy reconstruction in neutrino oscillation experiments, but these interactions have rarely been studied. MINERvA previously studied neutron production at an average antineutrino energy of ∼3 GeV in 2016 and found deficiencies in leading models. In this paper, the MINERvA 6 GeV average antineutrino energy dataset is shown to have similar disagreements. A measurement of the cross section for an antineutrino to produce two or more neutrons and have low visible energy is presented as an experiment-independent way to explore neutron production modeling. This cross section disagrees with several leading models’ predictions. Neutron modeling techniques from nuclear physics are used to quantify neutron detection uncertainties on this result. 

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