Abstract—Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, overheating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no
redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction—approaching 100% for multiple patterns.
Index Terms—Design for Testability (DFT), Low Power Test, On-Chip Decompressor
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Test Architecture for Fine Grained Capture Power Reduction
Excessive power during in–field testing can cause
multiple issues, including invalidation of the test results, overheating,
and damage to the circuit. In this paper, we evaluate
the reduction of capture power when specific segments of a
scan chain can be kept from capturing data subject to values
stored in a control register. The proposed approach requires no
changes to the Automatic Test Pattern Generation (ATPG), no
redesign of the circuitry to match a particular test set, and no
additional patterns to maintain fault coverage. We will show that
our approach can achieve very high capture power reduction—
approaching 100% for multiple patterns.
more »
« less
- Award ID(s):
- 1814928
- NSF-PAR ID:
- 10118879
- Date Published:
- Journal Name:
- IEEE International Conference on Electronics, Circuits and Systems (ICECS),
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.more » « less
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null (Ed.)Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.more » « less
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Conclusions Due to less multiple testing correction and noise reduction, haplotype based testing is able to outperform SNP based tests in terms of power in most scenarios.
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