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Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, overheating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction— approaching 100% for multiple patterns.
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Test Architecture for Fine Grained Capture Power Reduction
Abstract—Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, overheating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction—approaching 100% for multiple patterns. Index Terms—Design for Testability (DFT), Low Power Test, On-Chip Decompressor
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- Award ID(s):
- 1812777
- PAR ID:
- 10118883
- Date Published:
- Journal Name:
- Proc. of 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Accepted Manuscript1.0
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