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1. Harnessing Uncertainty in Photoresistor Sensor for True Random Number Generation in IoT Devices

   https://doi.org/10.1109/ICCE46568.2020.9042967  

   Degada, Amit; Thapliyal, Himanshu (January 2020, 2020 IEEE International Conference on Consumer Electronics (ICCE))

   null (Ed.)

   Internet of Things (IoT) has facilitated the connection of many smart devices via internet. Recent cyberattacks have shown that resource constrained IoT nodes are easy prey that lead towards compromising the secrecy of the data and vulnerabilities could be exploited remotely to take control of safety-critical systems. Photoresistor sensors have applications in IoT systems, such as smart street lighting, intelligent cameras, light activated smart consumer electronics, smart home, smart healthcare, etc. Building hardware security primitives, such as True Random Number Generator (TRNG), based on the intrinsic properties of photoresistor would be a novel direction to develop cost-savvy IoT security primitives. Therefore, this paper proposes a TRNG prototype that is devised from uncertainty presents in photoresistor sensors. The proposed TRNG prototype does not require any complex interfacing for preprocessing the weak signal, thereby reducing the unnecessary delay and the recurring hardware cost. The proposed prototype employs the novel approach of additive scrambling that aids to sample sensors at a higher rate. The proposed TRNG has an average random bit generation rate of 8 kbps that is better than the recent work in the literature. The quality of randomness was validated by 15 test batteries of NIST STS test. 

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2. Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin

   Bahar Talukder, B. M.; Menon, Vineetha; Ray, Biswajit; Neal, Tempestt; Rahman, Md Tauhidur (December 2020, 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST))

   Due to globalization in the semiconductor supply chain, counterfeit dynamic random-access memory (DRAM) chips/modules have been spreading worldwide at an alarming rate. Deploying counterfeit DRAM modules into an electronic system can severely affect security and reliability domains because of their sub-standard quality, poor performance, and shorter life span. Besides, studies suggest that a counterfeit DRAM can be more vulnerable to sophisticated attacks. However, detecting counterfeit DRAMs is very challenging because of their nature and ability to pass the initial testing. In this paper, we propose a technique to identify the DRAM origin (i.e., the origin of the manufacturer and the specification of individual DRAM) to detect and prevent counterfeit DRAM modules. A silicon evaluation shows that the proposed method reliably identifies off-the-shelf DRAM modules from three major manufacturers. 

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3. DRAM Retention Behavior with Accelerated Aging in Commercial Chips

   https://doi.org/10.3390/app12094332  

   Bepary, Md Kawser; Talukder, Bashir Mohammad; Rahman, Md Tauhidur (May 2022, Applied Sciences)

   The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error. 

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4. SELF: A High Performance and Bandwidth Efficient Approach to Exploiting Die-Stacked DRAM as Part of Memory

   https://doi.org/10.1109/MASCOTS.2017.23  

   Guo, Yuhua; Liu, Qing; Xiao, Weijun; Huang, Ping; Podhorszki, Norbert; Klasky, Scott; He, Xubin (September 2017, 2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS))

   Die-stacked DRAM (a.k.a., on-chip DRAM) provides much higher bandwidth and lower latency than off-chip DRAM. It is a promising technology to break the “memory wall”. Die-stacked DRAM can be used either as a cache (i.e., DRAM cache) or as a part of memory (PoM). A DRAM cache design would suffer from more page faults than a PoM design as the DRAM cache cannot contribute towards capacity of main memory. At the same time, obtaining high performance requires PoM systems to swap requested data to the die-stacked DRAM. Existing PoM designs fall into two categories - line-based and page-based. The former ensures low off-chip bandwidth utilization but suffers from a low hit ratio of on-chip memory due to limited temporal locality. In contrast, page-based designs achieve a high hit ratio of on-chip memory albeit at the cost of moving large amounts of data between on-chip and off-chip memories, leading to increased off-chip bandwidth utilization and significant system performance degradation. To achieve a similar high hit ratio of on-chip memory as pagebased designs, and eliminate excessive off-chip traffic involved, we propose SELF, a high performance and bandwidth efficient approach. The key idea is to SElectively swap Lines in a requested page that are likely to be accessed according to page Footprint, instead of blindly swapping an entire page. In doing so, SELF allows incoming requests to be serviced from the on-chip memory as much as possible, while avoiding swapping unused lines to reduce memory bandwidth consumption. We evaluate a memory system which consists of 4GB on-chip DRAM and 12GB offchip DRAM. Compared to a baseline system that has the same total capacity of 16GB off-chip DRAM, SELF improves the performance in terms of instructions per cycle by 26.9%, and reduces the energy consumption per memory access by 47.9% on average. In contrast, state-of-the-art line-based and page-based PoM designs can only improve the performance by 9.5% and 9.9%, respectively, against the same baseline system. 

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5. GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing

   https://doi.org/10.1145/3299874.3317984  

   Fan, Deliang; Angizi, Shaahin (May 2019, 2019 on Great Lakes Symposium on VLSI)

   In this paper, we propose GraphiDe, a novel DRAM-based processing-in-memory (PIM) accelerator for graph processing. It transforms current DRAM architecture to massively parallel computational units exploiting the high internal bandwidth of the modern memory chips to accelerate various graph processing applications. GraphiDe can be leveraged to greatly reduce energy consumption and latency dealing with underlying adjacency matrix computations by eliminating unnecessary off-chip accesses. The extensive circuit-architecture simulations over three social network data-sets indicate that GraphiDe achieves on average 3.1x energy-efficiency improvement and 4.2x speed-up over the recent DRAM based PIM platform. It achieves ~59x higher energy-efficiency and 83x speed-up over GPU-based acceleration methods. 

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