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Title: Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI
Award ID(s):
1730158
PAR ID:
10171018
Author(s) / Creator(s):
; ; ; ;
Date Published:
Journal Name:
Proceedings of Design, Automation and Test in Europe (DATE) Conference
Page Range / eLocation ID:
830 to 835
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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