skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.


Title: Silicon Photonic Microring Resonators: Design Optimization under Fabrication Non-uniformity
Microring resonators (MRRs) are very often considered as the primary building block in silicon photonic integrated circuits (PICs). Despite many advantages, MRRs are considerably sensitive to fabrication non-uniformity (a.k.a. fabrication process variations), necessitating the use of power-hungry compensation methods (e.g., thermal tuning) to guarantee their reliable operation. Moreover, the design space of MRRs is complicated and includes several highly correlated design parameters, preventing designers from easily exploring and optimizing the design of MRRs against fabrication process variations (FPVs). In this paper, for the first time, we present a comprehensive design space exploration and optimization of MRRs against FPVs. In particular, we indicate how physical design parameters in MRRs can be optimized during design time to enhance their tolerance to FPVs while also improving the insertion loss and quality factor in such devices. Fabrication results obtained by measuring multiple fabricated MRRs designed using our design optimization solution demonstrate a significant 70% improvement on average in MRRs tolerance to different FPVs. Such improvement indicates the efficiency of our novel design optimization solution in reducing the tuning power required for reliable operation of MRRs.  more » « less
Award ID(s):
1813370
PAR ID:
10190933
Author(s) / Creator(s):
; ; ;
Date Published:
Journal Name:
IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. Abstract The stiffness of robot legs greatly affects legged locomotion performance; tuning that stiffness, however, can be a costly and complex task. In this paper, we directly tune the stiffness of jumping robot legs using an origami-inspired laminate design and fabrication method. In addition to the stiffness coefficient described by Hooke’s law, the nonlinearity of the force-displacement curve can also be tuned by optimizing the geometry of the mechanism. Our method reduces the number of parts needed to realize legs with different stiffness while simplifying manual redesign effort, lowering the cost of legged robots while speeding up the design and optimization process. We have fabricated and tested the leg across six different stiffness profiles that vary both the nonlinearity and coefficient. Through a vertical jumping experiment actuated by a DC motor, we also show that proper tuning of the leg stiffness can result in an 18% improvement in lift-off speed and an increase of 19% in peak power output. 
    more » « less
  2. Broad-scale modeling and optimization play a vital role in the design of advanced power converters. Optimization is normally implemented via brute force iterations of design variables or utilizing metaheuristic techniques which are time consuming for a wide range of potential topologies, device implementations, and operating points. Recently, discrete time state-space modeling has shown merits in rapid analysis and generality to arbitrary circuit topologies but has not yet been utilized under rapid optimization techniques across multiple converter parameters. In this work, we investigate methods to incorporate rapid gradient-based optimization techniques to leverage discrete time state-space modeling and showcase the approach in the power converter design process. The method is validated on a 48-to-1V converter designed using the proposed techniques. 
    more » « less
  3. Latest algorithmic development has brought competitive classification accuracy for neural networks despite constraining the network parameters to ternary or binary representations. These findings show significant optimization opportunities to replace computationally-intensive convolution operations (based on multiplication) with more efficient and less complex operations such as addition. In hardware implementation domain, processing-in-memory architecture is becoming a promising solution to alleviate enormous energy-hungry data communication between memory and processing units, bringing considerable improvement for system performance and energy efficiency while running such large networks. In this paper, we review several of our recent works regarding Processing-in-Memory (PIM) accelerator based on Magnetic Random Access Memory computational sub-arrays to accelerate the inference mode of quantized neural networks using digital non-volatile memory rather than using analog crossbar operation. In this way, we investigate the performance of two distinct in-memory addition schemes compared to other digital methods based on processing-in-DRAM/GPU/ASIC design to tackle DNN power and memory wall bottleneck. 
    more » « less
  4. The tidal waves of modern electronic/electrical devices have led to increasing demands for ubiquitous application-specific power converters. A conventional manual design procedure of such power converters is computation- and labor-intensive, which involves selecting and connecting component devices, tuning component-wise parameters and control schemes, and iteratively evaluating and optimizing the design. To automate and speed up this design process, we propose an automatic framework that designs custom power converters from design specifications using Monte Carlo Tree Search. Specifically, the framework embraces the upper-confidence-bound-tree (UCT), a variant of Monte Carlo Tree Search, to automate topology space exploration with circuit design specification-encoded reward signals. Moreover, our UCT-based approach can exploit small offline data via the specially designed default policy and can run in parallel to accelerate topology space exploration. Further, it utilizes a hybrid circuit evaluation strategy to substantially reduce design evaluation costs. Empirically, we demonstrated that our framework could generate energy-efficient circuit topologies for various target voltage conversion ratios. Compared to existing automatic topology optimization strategies, the proposed method is much more computationally efficient—the sequential version can generate topologies with the same quality while being up to 67% faster. The parallelization schemes can further achieve high speedups compared to the sequential version. 
    more » « less
  5. Having a well-rounded fixed leg design for a quadruped inevitably limits performance across diverse tasks, while tunability enables specialization and leads to better performance. This paper introduces a sub-500-gram quadruped robot with a rich leg design space. Made with laminate design and fabrication techniques, its legs have a range of tunable design parameters, including leg length, transmission ratio, and passive parallel and series stiffness. The legs are also straightforward to model, low-cost, and fast to manufacture. We propose methods to span the leg’s feasible design space and construct simulation environments for training a locomotion policy with reinforcement learning to remove the need for manual controller design and tuning. This policy not only works across leg designs but also exploits the unique dynamics of each leg for better locomotion. A curation process is employed to select designs given performance goals, which is more interpretable than optimization and provides insights for design improvements and discoveries of design principles. Thanks to the tight integration of design, fabrication, simulation, and control, our proposed pipeline produces leg designs with performance that aligns with the simulation, while the learned locomotion policy can be used successfully on the real robot. The fast longitudinal running design reaches a maximum speed of 0.7 m/s or 5.4 body lengths per second, and the low cost of transport (COT) design has a COT of 0.3. 
    more » « less