Persistent memory presents a great opportunity for crash-consistent computing in large-scale computing systems. The ability to recover data upon power outage or crash events can significantly improve the availability of large-scale systems, while improving the performance of persistent data applications (e.g., database applications). However, persistent memory suffers from high write latency and requires specific programming model (e.g., Intel’s PMDK) to guarantee crash consistency, which results in long latency to persist data. To mitigate these problems, recent standards advocate for sufficient back-up power that can flush the whole cache hierarchy to the persistent memory upon detection of an outage, i.e., extending the persistence domain to include the cache hierarchy. In the secure NVM with extended persistent domain(EPD), in addition to flushing the cache hierarchy, extra actions need to be taken to protect the flushed cache data. These extra actions of secure operation could cause significant burden on energy costs and battery size. We demonstrate that naive implementations could lead to significantly expanding the required power holdup budget (e.g., 10.3x more operations than EPD system without secure memory support). The significant overhead is caused by memory accesses of secure metadata. In this paper, we present Horus, a novel EPD-aware secure memory implementation.more »
HOOP: Efficient Hardware-Assisted Out-of-Place Update for Non-Volatile Memory
Byte-addressable non-volatile memory (NVM) is a
promising technology that provides near-DRAM performance
with scalable memory capacity. However, it requires atomic
data durability to ensure memory persistency. Therefore, many
techniques, including logging and shadow paging, have been
proposed. However, most of them either introduce extra write
traffic to NVM or suffer from significant performance overhead
on the critical path of program execution, or even both.
In this paper, we propose a transparent and efficient hardware-assisted out-of-place update (HOOP) mechanism that supports
atomic data durability, without incurring much extra writes and
performance overhead. The key idea is to write the updated data
to a new place in NVM, while retaining the old data until the
updated data becomes durable. To support this, we develop a
lightweight indirection layer in the memory controller to enable
efficient address translation and adaptive garbage collection
for NVM. We evaluate HOOP with a variety of popular data
structures and data-intensive applications, including key-value
stores and databases. Our evaluation shows that HOOP achieves
low critical-path latency with small write amplification, which
is close to that of a native system without persistence support.
Compared with state-of-the-art crash-consistency techniques, it
improves application performance by up to 1.7×, while reducing
the write amplification by up to 2.1×. HOOP also demonstrates
scalable data recovery capability on multi-core systems.
- Publication Date:
- NSF-PAR ID:
- 10195216
- Journal Name:
- 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
- Page Range or eLocation-ID:
- 584 to 596
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1109/ISCA45697.2020.00055
