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1. Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms

   https://doi.org/10.1109/DCIS.2018.8681492  

   Zhang, Rui; Yang, Kexin; Liu, Taizhi; Milor, Linda (November 2018, Design of Circuits and Integrated Systems)

   Advanced FinFET SRAMs undergo reliability degradation due to various front-end and back-end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout models that are calibrated by accelerated test. With respect to testing, the accelerated conditions which can help separate the dominant wearout mechanisms related to circuit failure is crucial for model calibration and reliability prediction. In this paper, the estimation of optimal accelerated test regions for a 14nm FinFET SRAM under various wearout mechanisms is presented. The dominant regions for specific mechanisms are compared and analyzed for effective testing. It is observed that for our SRAM example circuit only bias temperature instability (BTI) and middle-of-line time-dependent dielectric breakdown (MTDDB) have test regions where their failures can be isolated, while the other mechanisms can’t be extracted individually due to acceptable regions’ overlap. Meanwhile, the SRAM cell activity distribution has a small influence on test regions and selectivity. 

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2. Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology

   https://doi.org/10.1109/DCIS.2018.8681497  

   Yang, Kexin; Zhang, Rui; Liu, Taizhi; Kim, Dae-Hyun; Milor, Linda (November 2018, Design of Circuits and Integrated Systems)

   This paper proposes a methodology to find optimal accelerated test regions for lifetime parameter estimation for not only the traditional reliability concern, frontend-of-line dielectric breakdown (FEOL TDDB), but also the newly emerging wearout mechanism, middle-of-line time dependent dielectric breakdown (MOL TDDB) in 14nm FinFET technology. The framework to find the optimal test regions is introduced; the error estimating methodology is discussed in detail. Three digital circuits are presented for evaluation and comparison. The optimal test regions depend on the circuit size as well as the types of standard cells in the circuits. To ensure accurate lifetime parameter estimation, both error from sampling and error from selectivity should be considered at the same time. As a general guideline, higher estimation accuracy will be achieved by testing gate TDDB lifetime parameters at higher voltages, while testing middle-of-line TDDB at higher temperatures. 

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3. Machine Learning for Detection of Competing Wearout Mechanisms

   https://doi.org/10.1109/IRPS.2019.8720533  

   Hsu, Shu-Han; Yang, Kexin; Milor, Linda (March 2019, IEEE International Reliability Physics Symposium)

   Because data from a variety of wearout mechanisms is confounded in circuits, we apply machine learning techniques to detect the parameters of competing failure mechanisms in ring oscillators, which more closely mimic circuit behavior than test structures. This is the first known application using data analysis to distinguish competing wearout mechanisms in circuit-level data. To quickly and efficiently analyze failure data, we propose to use maximum likelihood estimation to separately determine the parameters of each underlying distribution by only observing the time-to-failure of samples. The quasi-Newton method 

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4. Extraction of Wearout Model Parameters Using On-Line Test of an SRAM

   https://doi.org/10.1016/j.microrel.2020.113756  

   Hsu, S.-H.; Huang, Y.-Y.; Wu, Y.-D.; Yang, K.; Lin, L.-H.; Milor, L (November 2020, Microelectronics reliability)

   null (Ed.)

   To accurately determine the reliability of SRAMs, we propose a method to estimate the wearout parameters of FEOL TDDB using on-line data collected during operations. Errors in estimating lifetime model parameters are determined as a function of time, which are based on the available failure sample size. Systematic errors are also computed due to uncertainty in estimation of temperature and supply voltage during operations, as well as uncertainty in process parameters and use conditions. 

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5. Identification of failure modes from circuit samples with confounded causes of failure

   Hsu, S.-H. Huang (July 2019, IEEE International Symposium on On-Line Testing and Robust System Design)

   Circuits may fail in the field due to a wide variety of failure modes. If there are frequent failures in the field, circuits are returned to the manufacturer, and the causes of failure must be identified. The challenge is that wearout mechanisms are confounded in circuit and system-level failure data. Using such failure data, it is often hard to separate the underlying failure causes without time-consuming and expensive physical failure analysis. To distinguish the wearout mechanisms for each failure sample, we have developed a quick and low-cost methodology using maximum likelihood estimation and probability analysis to determine the origin of the failure distributions, region of error, and sorting accuracy. We apply our methodology to analyze the competing wearout mechanisms in 14nm FinFET ring oscillators, as an example, using simulation. We also consider the problem of Trojan detection. 

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