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Advanced FinFET SRAMs undergo reliability degradation due to various front-end and back-end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout models that are calibrated by accelerated test. With respect to testing, the accelerated conditions which can help separate the dominant wearout mechanisms related to circuit failure is crucial for model calibration and reliability prediction. In this paper, the estimation of optimal accelerated test regions for a 14nm FinFET SRAM under various wearout mechanisms is presented. The dominant regions for specific mechanisms are compared and analyzed for effective testing. It is observed that for our SRAM example circuit only bias temperature instability (BTI) and middle-of-line time-dependent dielectric breakdown (MTDDB) have test regions where their failures can be isolated, while the other mechanisms can’t be extracted individually due to acceptable regions’ overlap. Meanwhile, the SRAM cell activity distribution has a small influence on test regions and selectivity.
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Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology
This paper proposes a methodology to find optimal accelerated test regions for lifetime parameter estimation for not only the traditional reliability concern, frontend-of-line dielectric breakdown (FEOL TDDB), but also the newly emerging wearout mechanism, middle-of-line time dependent dielectric breakdown (MOL TDDB) in 14nm FinFET technology. The framework to find the optimal test regions is introduced; the error estimating methodology is discussed in detail. Three digital circuits are presented for evaluation and comparison. The optimal test regions depend on the circuit size as well as the types of standard cells in the circuits. To ensure accurate lifetime parameter estimation, both error from sampling and error from selectivity should be considered at the same time. As a general guideline, higher estimation accuracy will be achieved by testing gate TDDB lifetime parameters at higher voltages, while testing middle-of-line TDDB at higher temperatures.
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- Award ID(s):
- 1700914
- PAR ID:
- 10104486
- Date Published:
- Journal Name:
- Design of Circuits and Integrated Systems
- Page Range / eLocation ID:
- 1 to 6
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/DCIS.2018.8681497
