Title: A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC
This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform. more »« less
Akram, Najath; Madanayake, Arjuna; Venkatakrishnan, Satheesh B.; Volakis, John L.; Psychogiou, Dimitra; Marzetta, Thomas L.; Rappaport, Theodore S.
(, IEEE Space Hardware and Radio Conference (SPaRC))
null
(Ed.)
Abstract: Communication systems of the future will require hundreds of independent spatial channels achieved through dense antenna arrays connected to digital signal processing software defined radios. The cost and complexity of data converters are a significant concern with systems having hundreds of antennas. This paper explores frequency division multiplexing as an approach for augmenting the baseband signals of multiple antenna channels such that a single ADC can sample a multitude of antennas in an array. The approach is equally applicable to both massive MIMO and mm-wave digital wireless arrays. An example design based on Xilinx RF SoC for combining 4 antenna channels at 28 GHz into a single ADC is provided.
While millimeter-wave (mmWave) wireless has recently gained tremendous attention with the transition to 5G, developing a broadly accessible experimental infrastructure will allow the research community to make significant progress in this area. Hence, in this paper, we present the design and implementation of various programmable and open-access 28/60 GHz software-defined radios (SDRs), deployed in the PAWR COSMOS advanced wireless testbed. These programmable mmWave radios are based on the IBM 28 GHz 64-element dual-polarized phased array antenna module (PAAM) subsystem board and the Sivers IMA 60 GHz WiGig transceiver. These front ends are integrated with USRP SDRs or Xilinx RF-SoC boards, which provide baseband signal processing capabilities. Moreover, we present measurements of the TX/RX beamforming performance and example experiments (e.g., real-time channel sounding and RFNoC-based 802.11ad preamble detection), using the mmWave radios. Finally, we discuss ongoing enhancement and development efforts focusing on these radios.
Mondal, Susnata; Carley, Larry Richard; Paramesh, Jeyanandh
(, IEEE Journal of Solid-State Circuits)
null
(Ed.)
This paper presents a two-layer RF/analog weighting MIMO transceiver that comprises fully-connected (FC) multi-stream beamforming tiles in the RF-domain first layer, followed by a fully connected analog- or digital-domain baseband layer. The architecture mitigates the complexity versus spectral-efficiency tradeoffs of existing hybrid MIMO architectures and enables MIMO stream/user scalability, superior energy-efficiency, and spatial-processing flexibility. Moreover, multi-layer architectures with FC tiles inherently enable the co-existence of MIMO with carrier-aggregation and full-duplex beamforming. A compact, reconfigurable bidirectional circuit architecture is introduced, including a new Cartesian-combining/splitting beamforming receiver/transmitter, dual-band bidirectional beamforming network, dual-band frequency translation chains, and baseband Cartesian beamforming with an improved programmable gain amplifier design. A 28/37 GHz band, two-layer, eight-element, four-stream (with two FC-tiles) hybrid MIMO transceiver prototype is designed in 65-nm CMOS to demonstrate the above features. The prototype achieves accurate beam/null-steering capability, excellent area/power efficiency, and state-of-the-art TX/RX mode performance in two simultaneous bands while demonstrating multi-antenna (up to eight) multi-stream (up to four) over-the-air spatial multiplexing operation using proposed energy-efficient two-layer hybrid beamforming scheme.
Adamshick, Stephen; Govindarajulu, Sandhiya; Alwan, Elias.
(, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS))
null
(Ed.)
This paper presents a novel low loss 3D system in package (SiP) approach for achieving antenna-on-chip integration. Specifically, this design uses 3D through silicon via (TSV) technology to achieve a vertical SiP phased array radio. The fully integrated package consists of a digital baseband chip, a radio frequency integrated circuit (RFIC), and lastly a microstrip patch phased array. The 3D TSVs achieve an insertion loss of less than 0.4 dB/pair at millimeter-wave frequencies. The differential fed microstrip patch array achieves a return loss of 40 dB at a 60 GHz center frequency with 4 GHz instantaneous bandwidth. The antenna array achieves an E and H plane realized gain of 17.1 dBi for a 4×4 element design. In addition, this design approach enables individual fabrication of each element to maximize yield with low cost assembly using ball grid array (BGA) technology. Lastly, this design does not require special design rules that comprise either transistor or antenna performance as compared to other methods outlined in antenna on chip design.
Yan, Han; Ramesh, Sridhar; Gallagher, Timothy; Ling, Curtis; Cabric, Danijela
(, IEEE circuits and systems magazine)
Millimeter wave (mmW) communications is viewed as the key enabler of 5G cellular networks due to vast spectrum availability that could boost peak rate and capacity. Due to increased propagation loss in mmW band, transceivers with massive antenna array are required to meet a link budget, but their power consumption and cost become limiting factors for commercial systems. Radio designs based on hybrid digital and analog array architectures and the usage of radio frequency (RF) signal processing via phase shifters have emerged as potential solutions to improve radio energy efficiency and deliver performances close to the conventional digital antenna arrays. In this paper, we provide an overview of the state-of-the-art mmW massive antenna array designs and comparison among three array architectures, namely digital array, partially-connected hybrid array (sub-array), and fully-connected hybrid array. The comparison of performance, power, and area for these three architectures is performed for three representative 5G downlink use cases, which cover a range of pre-beamforming signal-to-noise-ratios (SNR) and multiplexing regimes. This is the first study to comprehensively model and quantitatively analyze all design aspects and criteria including: 1) optimal linear precoder, 2) impact of quantization error in digital-to-analog converter (DAC) and phase shifters, 3) RF signal distribution network, 4) power and area estimation based on state-of-the-art mmW circuits including baseband digital precoding, digital signal distribution network, high-speed DACs, oscillators, mixers, phase shifters, RF signal distribution network, and power amplifiers. Our simulation results show that the fully-digital array architecture is the most power and area efficient compared against optimized designs for sub-array and hybrid array architectures. Our analysis shows that digital array architecture benefits greatly from multi-user multiplexing. The analysis also reveals that sub-array architecture performance is limited by reduced beamforming gain due to array partitioning, while the system bottleneck of the fully-connected hybrid architecture is the excessively complicated and power hungry RF signal distribution network.
Sravan Pulipati, Viduneth Ariyarathna. A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC. Retrieved from https://par.nsf.gov/biblio/10205757. 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS) 2019.
Sravan Pulipati, Viduneth Ariyarathna. A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC. 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019 (). Retrieved from https://par.nsf.gov/biblio/10205757.
Sravan Pulipati, Viduneth Ariyarathna.
"A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC". 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS) 2019 (). Country unknown/Code not available. https://par.nsf.gov/biblio/10205757.
@article{osti_10205757,
place = {Country unknown/Code not available},
title = {A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC},
url = {https://par.nsf.gov/biblio/10205757},
abstractNote = {This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RFSoC solution installed on the Xilinx ZCU1275 prototyping platform.},
journal = {2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)},
volume = {2019},
author = {Sravan Pulipati, Viduneth Ariyarathna},
editor = {null}
}
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