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1. Exploring Thread Coarsening on FPGA

   https://doi.org/10.1109/HiPC53243.2021.00062  

   Zarch, Mostafa Eghbali; Neff, Reece; Becchi, Michela (January 2022, 2021 IEEE 28th International Conference on High Performance Computing, Data, and Analytics (HiPC))

   Over the past few years, there has been an increased interest in including FPGAs in data centers and high-performance computing clusters along with GPUs and other accelerators. As a result, it has become increasingly important to have a unified, high-level programming interface for CPUs, GPUs and FPGAs. This has led to the development of compiler toolchains to deploy OpenCL code on FPGA. However, the fundamental architectural differences between GPUs and FPGAs have led to performance portability issues: it has been shown that OpenCL code optimized for GPU does not necessarily map well to FPGA, often requiring manual optimizations to improve performance. In this paper, we explore the use of thread coarsening - a compiler technique that consolidates the work of multiple threads into a single thread - on OpenCL code running on FPGA. While this optimization has been explored on CPU and GPU, the architectural features of FPGAs and the nature of the parallelism they offer lead to different performance considerations, making an analysis of thread coarsening on FPGA worthwhile. Our evaluation, performed on our microbenchmarks and on a set of applications from open-source benchmark suites, shows that thread coarsening can yield performance benefits (up to 3-4x speedups) to OpenCL code running on FPGA at a limited resource utilization cost. 

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2. Memory access scheduling to reduce thread migrations

   https://doi.org/10.1145/3497776.3517768  

   Damani, Sana; Barua, Prithayan; Sarkar, Vivek (March 2022, ACM)
3. TSVD4J: Thread-Safety Violation Detection for Java

   https://doi.org/10.1109/ICSE-Companion58688.2023.00029  

   Rahman, Shanto; Li, Chengpeng; Shi, August (May 2023, IEEE)
4. Parallel Loop Locality Analysis for Symbolic Thread Counts

   https://doi.org/10.1145/3656019.3676948  

   Liu, Fangzhou; Zhu, Yifan; Sun, Shaotong; Ding, Chen; Smith, Wesley; Hosseini, Kaave Seyed (October 2024, ACM)
5. Bringing Inter-Thread Cache Benefits to Federated Scheduling

   https://doi.org/10.1109/RTAS48715.2020.00005  

   Tessler, Corey; Modekurthy, Venkata P.; Fisher, Nathan; Saifullah, Abusayeed (April 2020, Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS))

   Multiprocessor scheduling of hard real-time tasks modeled by directed acyclic graphs (DAGs) exploits the inherent parallelism presented by the model. For DAG tasks, a node represents a request to execute an object on one of the available processors. In one DAG task, there may be multiple execution requests for one object, each represented by a distinct node. These distinct execution requests offer an opportunity to reduce their combined cache overhead through coordinated scheduling of objects as threads within a parallel task. The goal of this work is to realize this opportunity by incorporating the cache-aware BUNDLE-scheduling algorithm into federated scheduling of sporadic DAG task sets.This is the first work to incorporate instruction cache sharing into federated scheduling. The result is a modification of the DAG model named the DAG with objects and threads (DAG-OT). Under the DAG-OT model, descriptions of nodes explicitly include their underlying executable object and number of threads. When possible, nodes assigned the same executable object are collapsed into a single node; joining their threads when BUNDLE-scheduled. Compared to the DAG model, the DAG-OT model with cache-aware scheduling reduces the number of cores allocated to individual tasks by approximately 20 percent in the synthetic evaluation and up to 50 percent on a novel parallel computing platform implementation. By reducing the number of allocated cores, the DAG-OT model is able to schedule a subset of previously infeasible task sets. 

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