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1. Heterogeneous Integration for Silicon Photonic Systems: Challenges and Approaches

   https://doi.org/10.1109/EDTM50988.2021.9420896  

   Dallesasse, John M.; Carlson, John A.; Ganjoo, Manaav; Espenhahn, Leah (April 2021, 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM))

   null (Ed.)

   Enhancing the functionality of silicon through the integration of other materials such as III-V semiconductors has been recognized as a path to overcoming limitations imposed by characteristics fundamental to silicon's material physics while still capitalizing on properties that have enabled the success of the global integrated circuit industry [1]–[2][3]. High-speed electronic devices, devices with high breakdown voltages, light emitting/detecting devices, and devices for photon control can all be integrated with conventional CMOS to perform specialized electronic or photonic functions if suitable methods for forming such heterogeneously integrated regions are available that provide high yield and are compatible with fabrication processes that occur subsequent to the heterogeneous integration process. Technical challenges include lattice mismatch, thermal expansion coefficient differences, having the capability to form low-resistance electrical contacts using materials that are compatible with CMOS, more generally managing cross-contamination in tools used for front-end-of-line processing after III-V regions are established on the silicon wafers, and thermal management for the heterogeneously integrated devices or circuits. These together create formidable obstacles, but there is also the obstacle of defining a business case for creating hybrid wafer fabs given the applications that would be served by ICs with enhanced functionality. Bringing functions that are off chip onto the chip needs to be justified both technically and financially. 

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2. 2-Phase Energy-Efficient Secure Positive Feedback Adiabatic Logic for CPA-Resistant IoT Devices

   https://doi.org/10.1109/WF-IoT48130.2020.9221065  

   Kahleifeh, Zachary; Thapliyal, Himanshu (June 2020, 2020 IEEE 6th World Forum on Internet of Things (WF-IoT))

   null (Ed.)

   Internet of Things (IoT) devices are mostly areas constrained and operate on a limited battery supply and therefore have tight energy budgets. Lightweight cryptography (LWC) such as PRESENT-80 allows for minimal area usage and low energy for secure operations. However, CMOS implemented LWCs are vulnerable to side-channel attacks such as Correlation Power Analysis (CPA). Adiabatic Logic is an emerging circuit design technique that can reduce energy consumption and be CPA resistant. Many existing adiabatic logic families use a 4-phase clocking scheme which pays a large area penalty. Thus, in this paper, we propose 2-EE-SPFAL, a 2-phase clocking scheme implementation of an existing adiabatic family known as EE-SPFAL. We explore 2-phase sinusoidal waves in terms of energy efficiency and security. To demonstrate energy savings and security against CPA attacks we construct one round of PRESENT-80 in both CMOS and 2-EE-SPFAL. Simulations were conducted using 45nm technology in Cadence Spectre. At 12.5MHz, our results show an average energy saving of 50% between CMOS and 2-EE-SPFAL. Furthermore, we performed a CPA attack on both the CMOS and 2-EE-SPFAL implementation and determined that the CMOS key could be retrieved while the adiabatic key was kept hidden. 

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3. Enhancing the flexibility and functionality of SCNs: demonstration of evolution toward any-core-access, nondirectional, and contentionless spatial channel cross-connects [Invited]

   https://doi.org/10.1364/JOCN.423997  

   Jinno, Masahiko; Ishikawa, Tsubasa; Kodama, Takahiro; Hasegawa, Hiroshi; Subramaniam, Suresh (July 2021, Journal of Optical Communications and Networking)

   A spatial channel network (SCN) was recently proposed toward the forthcoming spatial division multiplexing (SDM) era, in which the optical layer is explicitly evolved to the hierarchical SDM and wavelength division multiplexing layers, and an optical node is decoupled into a spatial cross-connect (SXC) and wavelength cross-connect to achieve an ultrahigh-capacity optical network in a highly economical manner. In this paper, we report feasibility demonstrations of an evolution scenario regarding the SCN architecture to enhance the flexibility and functionality of spatial channel networking from a simplefixed-core-accessanddirectionalspatial channel ring network to a multidegree,any-core-access,nondirectional, andcore-contentionlessmesh SCN. As key building blocks of SXCs, we introduce what we believe to be novel optical devices: a $1\times <\#comment/>2$multicore fiber (MCF) splitter, a core selector (CS), and a core and port selector (CPS). We construct free-space optics-based prototypes of these devices using five-core MCFs. Detailed performance evaluations of the prototypes in terms of the insertion loss (IL), polarization-dependent loss (PDL), and intercore cross talk (XT) are conducted. The results show that the prototypes provide satisfactorily low levels of IL, PDL, and XT. We construct a wide variety of reconfigurable spatial add/drop multiplexers (RSADMs) and SXCs in terms of node degree, interport cross-connection architecture, and add/drop port connectivity flexibilities. Such RSADMs/SXCs include a fixed-core-access and directional RSADM using a $1\times <\#comment/>2$MCF splitter; an any-core-access, nondirectional SXC with core-contention using a CS; and an any-core-access, nondirectional SXC without core-contention using a CPS. Bit error rate performance measurements for SDM signals that traverse the RSADMs/SXCs confirm that there is no or a very slight optical signal-to-noise-ratio penalty from back-to-back performance. We also experimentally show that the flexibilities in the add/drop port of the SXCs allow us to recover from a single or concurrent double link failure with a wide variety of options in terms of availability and cost-effectiveness. 

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4. Adiabatic Logic Based Energy-Efficient Security for Smart Consumer Electronics

   https://doi.org/10.1109/MCE.2020.3028046  

   Kahleifeh, Zachary; Thapliyal, Himanshu (January 2021, IEEE Consumer Electronics Magazine)

   null (Ed.)

   Smart consumer electronic devices are mostly area constrained and operate on a limited battery supply and therefore, have tight energy budgets. Lightweight Cryptography (LWC) such as PRESENT-80 allows for minimal area usage and low energy for secure operations. However, CMOS implemented LWCs are vulnerable to side-channel attacks such as Correlation Power Analysis (CPA). Adiabatic Logic is an emerging circuit design technique that can reduce energy consumption and be CPA resistant. Many existing adiabatic logic families use a 4-phase clocking scheme which pays a large area penalty. Thus, in this article, we introduce 2-EESPFAL, a 2-phase clocking scheme implementation of an existing adiabatic family known as EE-SPFAL. To show the applicability of 2-EE-SPFAL, we construct a 2-phase clock generator that remains energy efficient and secure. From 100 kHz to 25 MHz, our results show an average energy saving of 76.5% to 21.3% between CMOS and 2-EE-SPFAL. As a case study, we performed a CPA attack on both the CMOS and 2-EE-SPFAL implementation of PRESENT-80 and determined that the CMOS key could be retrieved while the adiabatic key was kept hidden. 

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5. A Novel Energy-Efficient Sinusoidal Power Clocking-Based Writing Circuitry for the Hybrid CMOS/MTJ Architecture

   https://doi.org/10.1109/TMAG.2024.3430120  

   Yang, Wu; Degada, Amit; Thapliyal, Himanshu (September 2024, IEEE Transactions on Magnetics)

   Spin transfer torque magnetic random access memory (STT-MRAM) offers a promising solution for low-power and high-density memory due to its compatibility with CMOS, higher density, scalable nature, and non-volatility. However, the higher energy required to write bit cells has remained a key challenge for its adaptation into battery-operated smart handheld devices. The existing low-energy writing solutions require additional complex control logic mechanisms, further constraining the available area. In this research, we propose a solution to design energy-efficient write circuits by incorporating two techniques together. First, we propose the sinusoidal power clocking mechanism replacing the DC power supply in the conventional CMOS design. Second, we propose three lookup table (LUT)-based control logic circuits and one write circuit to reduce the area and further minimize energy dissipation. The experimental results are verified over the case study implementations of 4×4 STT-MRAM macro designed using bit cell configurations: i) one transistor and one magnetic tunnel junction (MTJ) (1T-1MTJ) and ii) four transistors and two MTJs (4T-2MTJ). The post-layout simulation for the frequency range from 250 kHz to 6.25 MHz shows that the write circuit, which uses the proposed LUT-based control logic circuits and a write driver with a sinusoidal power supply, achieves more than a 65.05% average energy saving compared to the CMOS counterpart. Furthermore, the write circuit, which uses the proposed 6T write driver with the sinusoidal power supply, shows an improvement in energy saving by more than 70.60% compared to the CMOS counterpart. We also verified that the energy-saving performance remains relatively consistent with the change in temperature and the tunneling magnetoresistance (TMR) ratio. 

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