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1. Design, Construction, and Testing of the APOLLO ATCA Blades for Use at the HL-LHC

   Akpinar, Alp; Blaizot, Aymeric; Cholak, Serhii; de_Castro, Gianfranco; Demiragli, Zeynep; Duquette, Alec; Fulcher, Jonathan; Gastler, Dan; Hahn, Kristian; Hazen, Eric; et al (March 2025, arXiv)

   The Apollo Advanced Telecommunications Computing Architecture (ATCA) platform is an open-source design consisting of a generic "Service Module" (SM) and a customizable "Command Module" (CM), allowing for cost-effective use in applications such as the readout of the inner tracker and the Level-1 track trigger for the CMS Phase-II upgrade at the HL-LHC. The SM integrates an intelligent IPMC, robust power entry and conditioning systems, a powerful system-on-module computer, and flexible clock and communication infrastructure. The CM is designed around two Xilinx Ultrascale+ FPGAs and high-density, high-bandwidth optical transceivers capable of 25 Gb/s. Crates of Apollo blades are currently being tested at Boston University, Cornell University, and CERN. 

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2. The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3

   https://doi.org/10.1088/1748-0221/19/05/P05063  

   Aad, G; Abbott, B; Abbott, DC; Abdallah, J; Abeling, K; Abidi, SH; Aboulhorma, A; Abovyan, S; Abramowicz, H; Abreu, H; et al (May 2024, Journal of Instrumentation)

   Abstract The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of  ℒ = 2 × 10³⁴cm^-2s^-1was routinely achieved at the start of fills, twice the design luminosity. For Run 3, accelerator improvements, notably luminosity levelling, allow sustained running at an instantaneous luminosity of  ℒ = 2 × 10³⁴cm^-2s^-1, with an average of up to 60 interactions per bunch crossing. The ATLAS detector has been upgraded to recover Run 1 single-lepton trigger thresholds while operating comfortably under Run 3 sustained pileup conditions. A fourth pixel layer 3.3 cm from the beam axis was added before Run 2 to improve vertex reconstruction and b-tagging performance. New Liquid Argon Calorimeter digital trigger electronics, with corresponding upgrades to the Trigger and Data Acquisition system, take advantage of a factor of 10 finer granularity to improve triggering on electrons, photons, taus, and hadronic signatures through increased pileup rejection. The inner muon endcap wheels were replaced by New Small Wheels with Micromegas and small-strip Thin Gap Chamber detectors, providing both precision tracking and Level-1 Muon trigger functionality. Trigger coverage of the inner barrel muon layer near one endcap region was augmented with modules integrating new thin-gap resistive plate chambers and smaller-diameter drift-tube chambers. Tile Calorimeter scintillation counters were added to improve electron energy resolution and background rejection. Upgrades to Minimum Bias Trigger Scintillators and Forward Detectors improve luminosity monitoring and enable total proton-proton cross section, diffractive physics, and heavy ion measurements. These upgrades are all compatible with operation in the much harsher environment anticipated after the High-Luminosity upgrade of the LHC and are the first steps towards preparing ATLAS for the High-Luminosity upgrade of the LHC. This paper describes the Run 3 configuration of the ATLAS detector. 

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3. HDRLPIM: A Simulator for Hyper-Dimensional Reinforcement Learning Based on Processing In-Memory

   https://doi.org/10.1145/3695875  

   Rakka, Mariam; Amer, Walaa; Chen, Hanning; Imani, Mohsen; Kurdahi, Fadi (October 2024, ACM Journal on Emerging Technologies in Computing Systems)

   Processing In-Memory (PIM) is a data-centric computation paradigm that performs computations inside the memory, hence eliminating the memory wall problem in traditional computational paradigms used in Von-Neumann architectures. The associative processor, a type of PIM architecture, allows performing parallel and energy-efficient operations on vectors. This architecture is found useful in vector-based applications such as Hyper-Dimensional (HDC) Reinforcement Learning (RL). HDC is rising as a new powerful and lightweight alternative to costly traditional RL models such as Deep Q-Learning. The HDC implementation of Q-Learning relies on encoding the states in a high-dimensional representation where calculating Q-values and finding the maximum one can be done entirely in parallel. In this article, we propose to implement the main operations of a HDC RL framework on the associative processor. This acceleration achieves up to\(152.3\times\)and\(6.4\times\)energy and time savings compared to an FPGA implementation. Moreover, HDRLPIM shows that an SRAM-based AP implementation promises up to\(968.2\times\)energy-delay product gains compared to the FPGA implementation. 

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4. Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors

   Liu, Y; Jin, Y; Li, P (July 2017, Proceedings - International Symposium on Low Power Electronics and Design)

   As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its FPGA implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed FPGA-based neural processor system is up to 29% more energy efficient than a baseline LSM processor with little extra hardware overhead. 

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5. A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs

   https://doi.org/DOI 10.1109/ISVLSI.2018.00031  

   Bu, Lake; Mark, Miguel; Kinsy, Michel A. (July 2018, Proceedings)

   Over the next decade, processor design will encounter a number of challenges. The ongoing miniaturization of semiconductor manufacturing technologies that has enabled the integration of hundreds to thousands of processing cores on a single chip is pushing the limits of physical laws. The fabrication process has also grown more complex and globalized with widespread use of third-party IPs (intellectual properties). This development ecosystem has complicated the security and trust view of processors. Some of the pressing processor architecture design questions are: (1) how to use reconfiguration and redundancy to improve reliability without introducing additional and potentially insecure system states, (2) what analytical models lend themselves best to the joint implementation of reliability and security in these systems, and (3) how to optimally and securely share resources and data among processing elements with high degree of reliability. In this work, we present and discuss (1) principal reliability approaches - error correction code, modular redundancy, (2) processor architecture specific reliability, (3) major secure processor architectures. We also highlight key features of a small representative class of the secure and reliable architectures. 

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