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1. Visible Light Communication Cyber-Physical Systems-on-Chip for Smart Cities

   Zijin, Pan; Tian, Lang; Cheng, Li; Mengfu, Di; Gang, Chen; Yehuda, Kalay; Ramdas, Pai; Albert, Wang (December 2019, Proc. 2nd IEEE International Conference on Information Communication and Signal Processing (ICSP))

   null (Ed.)

   This paper reviews recent developments of Light Emitting Diode (LED) based Visible Light Communication (VLC) technologies and related cyber-physical systems-on-chip (CPSoC) for smart city applications. Critical aspects of LED VLC cyber-physical systems are discussed. Designs of LEDbased VLC CPSoC Integrated Circuits (IC) are depicted. LED VLC technology, as a viable internet of things (IoT) solution, has the potential for various applications for smart cities including smart hospitals, smart homes, smart communities and smart traffics in near future. 

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2. Topological on-chip lasers

   https://doi.org/10.1063/5.0150421  

   Li, Zhitong; Luo, Xi-Wang; Gu, Qing (July 2023, APL Photonics)

   A miniature on-chip laser is an essential component of photonic integrated circuits for a plethora of applications, including optical communication and quantum information processing. However, the contradicting requirements of small footprint, robustness, single-mode operation, and high output power have led to a multi-decade search for the optimal on-chip laser design. During this search, topological phases of matter—conceived initially in electronic materials in condensed matter physics—were successfully extended to photonics and applied to miniature laser designs. Benefiting from the topological protection, a topological edge mode laser can emit more efficiently and more robustly than one emitting from a trivial bulk mode. In addition, single-mode operation over a large range of excitation energies can be achieved by strategically manipulating topological modes in a laser cavity. In this Perspective, we discuss the recent progress of topological on-chip lasers and an outlook on future research directions. 

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3. Design of a Multi-layered On-chip Wireless Power Transfer (WPT) System Design for Brain Neuromodulation Applications

   https://doi.org/10.1109/WMCS49442.2020.9172383  

   Biswas, Dipon K.; Rangel, Bernabe; Mahbub, Ifana (May 2020, 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS))

   null (Ed.)

   Chronic pain is a common disease and as a negative consequence can cause paralysis to an individual in the long run. Noninvasive brain stimulation is an effective method to reduce pain in the short term. However, for long-term treatment, neural data analysis along with the stimulation is highly desirable. In this work, a unique multilayer spiral coil with a total dimension of 500 μm×500 μm is designed in a 0.5 μm CMOS process to make it suitable for a fully implantable system. The electrical modeling of the coil is also analyzed and simulated using Keysight's Advanced Design System (ADS) software to compare the theoretical modeling results with the simulation results. The electromagnetic (EM) simulation to characterize the on-chip coil in-terms of scattering parameters (S-parameters), Q -factor, power transfer efficiency (PTE) is performed using the Ansys High-Frequency Structure Simulator (HFSS) software. The operating frequency of the WPT system is chosen to be within 402-405 MHz which is the Medical Implant Communication System (MICS) band. The simulated Q -factor of the proposed on-chip coil is approximately 15 at 402 MHz. The on-chip coil is integrated with an on-chip seven-stage rectifier and some commercial off-the-shelf (COTS) components such as a DC-DC converter and a μ LED to design the complete optogenetic neuro-stimulation system. A minimum power transfer efficiency (PTE) of 0.4% is achieved through a 16 mm thick tissue media using the proposed WPT system. With that efficiency, the proposed system is able to provide constant power to light up a μ LED and proves to be a good candidate for neuromodulation applications. 

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4. Low Loss Chip-to-Chip Couplers for High Density Co-Packaged Optics

   https://doi.org/10.1364/opticaopen.25852735.v1  

   Weninger, Drew; Otálvaro, Samuel Serna; Ranno, Luigi; Kimerling, Lionel; Agarwal, Anuradha (May 2024, Optica Open)

   An experimentally demonstrated, vertical chip-to-chip evanescent coupler between silicon nitride (Si₃N₄) and silicon (Si) is presented with the coupler loss measured to be 0.39 ± 1.06 dB at 1550 nm with a 1-dB bandwidth of 160 nm extending across the C-band, S-band, and L-band (1480-1640 nm). The average coupling loss was determined to be 0.73 dB for the 1480-1640 nm wavelength range with a ± 2σ tolerance of ± 0.92 dB. The 1-dB lateral alignment tolerance was 1.56 ± 0.14 μm at 1550 nm and the average tolerance was 1.38 ± 0.24 μm across the 1480-1640 nm wavelength regime. In addition, the average coupling loss varied by less than ± 0.35 dB and the average 1-dB alignment tolerance varied by less than ± 30 nm for temperatures varying from 23-60°C. Finally, the average coupling loss range was less than 1.5 dB range across four sets of identically packaged die. This is the first experimental demonstration of an inter-chip, passively assembled evanescent coupler using standard CMOS foundry processes for directly coupling between Si and Si₃N₄, overcoming a waveguide refractive index difference of Δn = 1.32 without requiring taper tip widths of less than 100 nm. 

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5. Reconfigurable Network-on-Chip Security Architecture

   https://doi.org/10.1145/3406661  

   Charles, Subodha; Mishra, Prabhat (October 2020, ACM Transactions on Design Automation of Electronic Systems)

   null (Ed.)

   Growth of the Internet-of-things has led to complex system-on-chips (SoCs) being used in the edge devices in IoT applications. The increased complexity is demanding designers to consider several critical factors, such as dynamic requirement changes, long application life, mass production, and tight time-to-market deadlines. These requirements lead to more complex security concerns. SoC manufacturers outsource some of the intellectual property cores integrated on the SoC to untrusted third-party vendors. The untrusted intellectual properties can contain malicious implants, which can launch attacks using the resources provided by the on-chip interconnection network, commonly known as the network-on-chip (NoC). Existing efforts on securing NoC have considered lightweight encryption, authentication, and other attack detection mechanisms such as denial-of-service and buffer overflows. Unfortunately, these approaches focus on designing statically optimized security solutions. As a result, they are not suitable for many IoT systems with long application life and dynamic requirement changes. There is a critical need to design reconfigurable security architectures that can be dynamically tuned based on changing requirements. In this article, we propose a tier-based reconfigurable security architecture that can adapt to different use-case scenarios. We explore how to design an efficient reconfigurable architecture that can support three popular NoC security mechanisms (encryption, authentication, and denial-of-service attack detection and localization) and implement suitable dynamic reconfiguration techniques. We evaluate our proposed framework by running standard benchmarks enabling different tiers of security and provide a comprehensive analysis of how different levels of security can affect application performance, energy efficiency, and area overhead. 

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