Cloud deployments now increasingly exploit Field-Programmable Gate Array (FPGA) accelerators as part of virtual instances. While cloud FPGAs are still essentially single-tenant, the growing demand for efficient hardware acceleration paves the way to FPGA multi-tenancy. It then becomes necessary to explore architectures, design flows, and resource management features that aim at exposing multi-tenant FPGAs to the cloud users. In this article, we discuss a hardware/software architecture that supports provisioning space-shared FPGAs in Kernel-based Virtual Machine (KVM) clouds. The proposed hardware/software architecture introduces an FPGA organization that improves hardware consolidation and support hardware elasticity with minimal data movement overhead. It also relies on VirtIO to decrease communication latency between hardware and software domains. Prototyping the proposed architecture with a Virtex UltraScale+ FPGA demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization, which is one of the goals of virtualization. Overall, our FPGA design achieved about 2× higher maximum frequency than the state of the art and a bandwidth reaching up to 28 Gbps on 32-bit data width.
Domain Isolation in FPGA-Accelerated Cloud and Data Center Applications
Cloud and data center applications increasingly leverage FPGAs
because of their performance/watt benefits and flexibility advantages over traditional processing cores such as CPUs and GPUs.
As the rising demand for hardware acceleration gradually leads to
FPGA multi-tenancy in the cloud, there are rising concerns about
the security challenges posed by FPGA virtualization. Exposing
space-shared FPGAs to multiple cloud tenants may compromise
the confidentiality, integrity, and availability of FPGA-accelerated
applications. In this work, we present a hardware/software architecture for domain isolation in FPGA-accelerated clouds and data
centers with a focus on software-based attacks aiming at unauthorized access and information leakage. Our proposed architecture
implements Mandatory Access Control security policies from software down to the hardware accelerators on FPGA. Our experiments
demonstrate that the proposed architecture protects against such
attacks with minimal area and communication overhead.
- Award ID(s):
- 2007320
- Publication Date:
- NSF-PAR ID:
- 10287874
- Journal Name:
- Proceedings of the 2021 on Great Lakes Symposium on VLSI. 2021
- Page Range or eLocation-ID:
- 283 to 288
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Publisher's Version of Record
- https://doi.org/10.1145/3453688.3461527
