More Like this

1. Implementation of multilayer perceptron network with highly uniform passive memristive crossbar circuits

   https://doi.org/10.1038/s41467-018-04482-4  

   Bayat, F. Merrikh ; Prezioso, M. ; Chakrabarti, B. ; Nili, H. ; Kataeva, I. ; Strukov, D. ( June 2018 , Nature Communications)

   The progress in the field of neural computation hinges on the use of hardware more efficient than the conventional microprocessors. Recent works have shown that mixed-signal integrated memristive circuits, especially their passive (0T1R) variety, may increase the neuromorphic network performance dramatically, leaving far behind their digital counterparts. The major obstacle, however, is immature memristor technology so that only limited functionality has been reported. Here we demonstrate operation of one-hidden layer perceptron classifier entirely in the mixed-signal integrated hardware, comprised of two passive 20 × 20 metal-oxide memristive crossbar arrays, board-integrated with discrete conventional components. The demonstrated network, whose hardware complexity is almost 10× higher as compared to previously reported functional classifier circuits based on passive memristive crossbars, achieves classification fidelity within 3% of that obtained in simulations, when using ex-situ training. The successful demonstration was facilitated by improvements in fabrication technology of memristors, specifically by lowering variations in theirI–Vcharacteristics.

    

   more » « less
2. (Digital Presentation) Oxide Memristors Based on SiO 2 with Cu/Ag Alloy Metallization for Neuromorphic Computing

   https://doi.org/10.1149/MA2022-0215808mtgabs  

   Qin, Fei ; Song, Han Wook ; Qin, Fei ( October 2022 , ECS Meeting Abstracts)

   By mimicking biomimetic synaptic processes, the success of artificial intelligence (AI) has been astounding with various applications such as driving automation, big data analysis, and natural-language processing.[1-4] Due to a large quantity of data transmission between the separated memory unit and the logic unit, the classical computing system with von Neumann architecture consumes excessive energy and has a significant processing delay.[5] Furthermore, the speed difference between the two units also causes extra delay, which is referred to as the memory wall.[6, 7] To keep pace with the rapid growth of AI applications, enhanced hardware systems that particularly feature an energy-efficient and high-speed hardware system need to be secured. The novel neuromorphic computing system, an in-memory architecture with low power consumption, has been suggested as an alternative to the conventional system. Memristors with analog-type resistive switching behavior are a promising candidate for implementing the neuromorphic computing system since the devices can modulate the conductance with cycles that act as synaptic weights to process input signals and store information.[8, 9]

   The memristor has sparked tremendous interest due to its simple two-terminal structure, including top electrode (TE), bottom electrode (BE), and an intermediate resistive switching (RS) layer. Many oxide materials, including HfO₂, Ta₂O₅, and IGZO, have extensively been studied as an RS layer of memristors. Silicon dioxide (SiO₂) features 3D structural conformity with the conventional CMOS technology and high wafer-scale homogeneity, which has benefited modern microelectronic devices as dielectric and/or passivation layers. Therefore, the use of SiO₂as a memristor RS layer for neuromorphic computing is expected to be compatible with current Si technology with minimal processing and material-related complexities.

   In this work, we proposed SiO₂-based memristor and investigated switching behaviors metallized with different reduction potentials by applying pure Cu and Ag, and their alloys with varied ratios. Heavily doped p-type silicon was chosen as BE in order to exclude any effects of the BE ions on the memristor performance. We previously reported that the selection of TE is crucial for achieving a high memory window and stable switching performance. According to the study which compares the roles of Cu (switching stabilizer) and Ag (large switching window performer) TEs for oxide memristors, we have selected the TE materials and their alloys to engineer the SiO₂-based memristor characteristics. The Ag TE leads to a larger memory window of the SiO₂memristor, but the device shows relatively large variation and less reliability. On the other hand, the Cu TE device presents uniform gradual switching behavior which is in line with our previous report that Cu can be served as a stabilizer, but with small on/off ratio.[9] These distinct performances with Cu and Ag metallization leads us to utilize a Cu/Ag alloy as the TE. Various compositions of Cu/Ag were examined for the optimization of the memristor TEs. With a Cu/Ag alloying TE with optimized ratio, our SiO₂based memristor demonstrates uniform switching behavior and memory window for analog switching applications. Also, it shows ideal potentiation and depression synaptic behavior under the positive/negative spikes (pulse train).

   In conclusion, the SiO₂memristors with different metallization were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of memristor, we integrated Cu, Ag and Cu/Ag alloy as TEs and compared the switch characteristics. Our encouraging results clearly demonstrate that SiO₂with Cu/Ag is a promising memristor device with synaptic switching behavior in neuromorphic computing applications.

   Acknowledgement

   This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 22011044) by KRISS.

   References

   [1] Younget al.,IEEE Computational Intelligence Magazine,vol. 13, no. 3, pp. 55-75, 2018.

   [2] Hadsellet al.,Journal of Field Robotics,vol. 26, no. 2, pp. 120-144, 2009.

   [3] Najafabadiet al.,Journal of Big Data,vol. 2, no. 1, p. 1, 2015.

   [4] Zhaoet al.,Applied Physics Reviews,vol. 7, no. 1, 2020.

   [5] Zidanet al.,Nature Electronics,vol. 1, no. 1, pp. 22-29, 2018.

   [6] Wulfet al.,SIGARCH Comput. Archit. News,vol. 23, no. 1, pp. 20–24, 1995.

   [7] Wilkes,SIGARCH Comput. Archit. News,vol. 23, no. 4, pp. 4–6, 1995.

   [8] Ielminiet al.,Nature Electronics,vol. 1, no. 6, pp. 333-343, 2018.

   [9] Changet al.,Nano Letters,vol. 10, no. 4, pp. 1297-1301, 2010.

   [10] Qinet al., Physica Status Solidi (RRL) - Rapid Research Letters, pssr.202200075R1, In press, 2022.

    

   more » « less
3. An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM

   https://doi.org/10.1109/ISLPED.2019.8824944  

   Yuan, Geng ; Ma, Xiaolong ; Ding, Caiwen ; Lin, Sheng ; Zhang, Tianyun ; Jalali, Zeinab S. ; Zhao, Yilong ; Jiang, Li ; Soundarajan, Sucheta ; Wang, Yanzhi ( January 2019 , IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED))

   The high computation and memory storage of large deep neural networks (DNNs) models pose intensive challenges to the conventional Von-Neumann architecture, incurring substantial data movements in the memory hierarchy. The memristor crossbar array has emerged as a promising solution to mitigate the challenges and enable low-power acceleration of DNNs. Memristor-based weight pruning and weight quantization have been separately investigated and proven effectiveness in reducing area and power consumption compared to the original DNN model. However, there has been no systematic investigation of memristor-based neuromorphic computing (NC) systems considering both weight pruning and weight quantization. In this paper, we propose an unified and systematic memristor-based framework considering both structured weight pruning and weight quantization by incorporating alternating direction method of multipliers (ADMM) into DNNs training. We consider hardware constraints such as crossbar blocks pruning, conductance range, and mismatch between weight value and real devices, to achieve high accuracy and low power and small area footprint. Our framework is mainly integrated by three steps, i.e., memristor- based ADMM regularized optimization, masked mapping and retraining. Experimental results show that our proposed frame- work achieves 29.81× (20.88×) weight compression ratio, with 98.38% (96.96%) and 98.29% (97.47%) power and area reduction on VGG-16 (ResNet-18) network where only have 0.5% (0.76%) accuracy loss, compared to the original DNN models. We share our models at anonymous link http://bit.ly/2Jp5LHJ . 

   more » « less
4. Dual‐Gated MoS 2 Memtransistor Crossbar Array

   https://doi.org/10.1002/adfm.202003683  

   Lee, Hong‐Sub ; Sangwan, Vinod K. ; Rojas, William A. Gaviria ; Bergeron, Hadallia ; Jeong, Hye Yun ; Yuan, Jiangtan ; Su, Katherine ; Hersam, Mark C. ( September 2020 , Advanced Functional Materials)

   Memristive systems offer biomimetic functions that are being actively explored for energy‐efficient neuromorphic circuits. In addition to providing ultimate geometric scaling limits, 2D semiconductors enable unique gate‐tunable responses including the recent realization of hybrid memristor and transistor devices known as memtransistors. In particular, monolayer MoS₂memtransistors exhibit nonvolatile memristive switching where the resistance of each state is modulated by a gate terminal. Here, further control over the memtransistor neuromorphic response through the introduction of a second gate terminal is gained. The resulting dual‐gated memtransistors allow tunability over the learning rate for non‐Hebbian training where the long‐term potentiation and depression synaptic behavior is dictated by gate biases during the reading and writing processes. Furthermore, the electrostatic control provided by dual gates provides a compact solution to the sneak current problem in traditional memristor crossbar arrays. In this manner, dual gating facilitates the full utilization and integration of memtransistor functionality in highly scaled crossbar circuits. Furthermore, the tunability of long‐term potentiation yields improved linearity and symmetry of weight update rules that are utilized in simulated artificial neural networks to achieve a 94% recognition rate of hand‐written digits.

    

   more » « less
5. ECRAM Materials, Devices, Circuits and Architectures: A Perspective

   https://doi.org/10.1002/adma.202204771  

   Talin, A. Alec ; Li, Yiyang ; Robinson, Donald A. ; Fuller, Elliot J. ; Kumar, Suhas ( November 2022 , Advanced Materials)

   Non‐von‐Neumann computing using neuromorphic systems based on two‐terminal resistive nonvolatile memory elements has emerged as a promising approach, but its full potential has not been realized due to the lack of materials and devices with the appropriate attributes. Unlike memristors, which require large write currents to drive phase transformations or filament growth, electrochemical random access memory (ECRAM) decouples the “write” and “read” operations using a “gate” electrode to tune the conductance state through charge‐transfer reactions, and every electron transferred through the external circuit in ECRAM corresponds to the migration of ≈1 ion used to store analogue information. Like static dopants in traditional semiconductors, electrochemically inserted ions modulate the conductivity by locally perturbing a host's electronic structure; however, ECRAM does so in a dynamic and reversible manner. The resulting change in conductance can span orders of magnitude, from gradual increments needed for analog elements, to large, abrupt changes for dynamically reconfigurable adaptive architectures. In this in‐depth perspective, the history of ECRAM, the recent progress in devices spanning organic, inorganic, and 2D materials, circuits, architectures, the rich portfolio of challenging, fundamental questions, and how ECRAM can be harnessed to realize a new paradigm for low‐power neuromorphic computing are discussed.

    

   more » « less