Abstract—Human activity recognition (HAR) is a challenging area of research with many applications in human-computer interaction. With advances in artificial neural networks (ANNs), methods of HAR feature extraction from wearable sensor data have greatly improved and have increased interest in their classification using ANNs. Most prior work has only investigated the software implementations of ANN-based HAR. Here, we investigate, for the first time, two novel hardware implementations for use in resource-constrained edge devices. Through architecture exploration, we identify first a hybrid ANN we call DCLSTM incorporating the convolutional and long-short-term memory techniques. The second is a much more compact implementation WCLSTM that uses wavelet transforms (WTs) to enhance feature extraction; it can achieve even better accuracy while being smaller and simpler; it is therefore the better choice for resource-constrained applications. We present hardware implementations of these ANNs and evaluate their performance and resource utilization on the UCI HAR and WISDM datasets. Synthesis results on an FPGA platform show the superiority of the WT-assisted version in accuracy and size. Moreover, our networks achieve a better accuracy than earlier published works.
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Radio Frequency Fingerprinting on the Edge
Deep learning methods have been very successful
at radio frequency fingerprinting tasks, predicting the identity
of transmitting devices with high accuracy. We study radio frequency fingerprinting deployments at resource-constrained edge
devices. We use structured pruning to jointly train and sparsify
neural networks tailored to edge hardware implementations. We
compress convolutional layers by a 27.2× factor while incurring
a negligible prediction accuracy decrease (less than 1%). We
demonstrate the efficacy of our approach over multiple edge
hardware platforms, including a Samsung Galaxy S10 phone and
a Xilinx-ZCU104 FPGA. Our method yields significant inference
speedups, 11.5× on the FPGA and 3× on the smartphone, as
well as high efficiency: the FPGA processing time is 17× smaller
than in a V100 GPU. To the best of our knowledge, we are the
first to explore the possibility of compressing networks for radio
frequency fingerprinting; as such, our experiments can be seen as
a means of characterizing the informational capacity associated
with this specific learning task.
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- NSF-PAR ID:
- 10293165
- Date Published:
- Journal Name:
- IEEE Transactions on Mobile Computing
- ISSN:
- 1536-1233
- Page Range / eLocation ID:
- 1 to 1
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1109/TMC.2021.3064466
