skip to main content

Title: A Circuit for Simultaneous Reception of Data and Power using a Solar Cell
This paper presents a circuit for simultaneous reception of optical power and data using a solar cell. The circuit employs a switched-inductor boost DC-DC converter for energy harvesting and a low-power thresholding receiver for data reception. The thresholding data receiver comprises a current-sense resistor that monitors the current output of the solar cell, an instrumentation amplifier, a band-pass filter and a comparator. A system-level analysis of an optical communication system employing the proposed circuit is presented along with a circuit-level analysis and implementation. As a proof-of-concept, the proposed circuit for simultaneous power and data reception is implemented using off-the-shelf components and tested using a custom-built test setup. Measurement results, including harvested power, electronic noise and bit error rate (BER), are reported for a GaAs solar cell and a red LED light source. Results show that 223 μW of power are harvested by the DC-DC converter at a distance of 32.5 cm and a radiated power of 9.3 mW. At a modulation depth of 50% and a transmission speed of 2.5 kbps, a BER of 1.008×10^-3 is achieved. Measurement results reveal that the proposed solution exhibits a trade-off between harvested power, transmission speed and BER.
Authors:
; ; ; ; ; ;
Award ID(s):
1809637
Publication Date:
NSF-PAR ID:
10297622
Journal Name:
IEEE Transactions on Green Communications and Networking
Page Range or eLocation-ID:
1 to 10
ISSN:
2473-2400
Sponsoring Org:
National Science Foundation
More Like this
  1. This paper presents a single-aperture, single-pixel reader for communication with Optical Frequency Identification (OFID) tags. OFID tags use solar cells to transmit and receive information wirelessly as well as to harvest radiant energy. Due to its single-aperture architecture, the reader's optical system provides a shared optical path for reception and transmission. Also, physical alignment between the reader and an OFID tag is visually guided using the reader's emitted light, securing a robust data link as long as the OFID tag is illuminated. In this paper, a description of the reader's optical and electronic sub-systems are presented. The transmitter and receivermore »circuits are described in detail. The transmitter, built with a linear LED driver, achieves a power efficiency of nearly 87%. The receiver, featuring a third-order bandpass filter, reduces both low-frequency and high-frequency ambient noise. A prototype of the reader was fabricated and housed in a custom 3D-printed enclosure. Test results show that the reader is able to receive modulated luminescent signals from an OFID tag at a distance of 1 m and at a data rate of 3 kbps.« less
  2. Photonic network-on-chip (PNoC) architectures employ photonic links with dense wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers. Unfortunately, increasing the DWDM degree (i.e., using a larger number of wavelengths) to achieve a higher aggregated data rate in photonic links and, hence, higher throughput in PNoCs, requires sophisticated and costly laser sources along with extra photonic hardware. This extra hardware can introduce undesired noise to the photonic link and increase the bit error rate (BER), power, and area consumption of PNoCs. To mitigate these issues, the use of 4-pulse amplitude modulation (4-PAM) signaling, instead of the conventional on-off keying (OOK)more »signaling, can halve the wavelength signals utilized in photonic links for achieving the target aggregate data rate while reducing the overhead of crosstalk noise, BER, and photonic hardware. There are various designs of 4-PAM modulators reported in the literature. For example, the signal superposition (SS)–, electrical digital-to-analog converter (EDAC)–, and optical digital-to-analog converter (ODAC)–based designs of 4-PAM modulators have been reported. However, it is yet to be explored how these SS-, EDAC-, and ODAC-based 4-PAM modulators can be utilized to design DWDM-based photonic links and PNoC architectures. In this article, we provide a systematic analysis of the SS, EDAC, and ODAC types of 4-PAM modulators from prior work with regards to their applicability and utilization overheads. We then present a heuristic-based search method to employ these 4-PAM modulators for designing DWDM-based SS, EDAC, and ODAC types of 4-PAM photonic links with two different design goals: (i) to attain the desired BER of 10 -9 at the expense of higher optical power and lower aggregate data rate and (ii) to attain maximum aggregate data rate with the desired BER of 10 -9 at the expense of longer packet transfer latency. We then employ our designed 4-PAM SS–, 4-PAM EDAC–, 4-PAM ODAC–, and conventional OOK modulator–based photonic links to constitute corresponding variants of the well-known CLOS and SWIFT PNoC architectures. We eventually compare our designed SS-, EDAC-, and ODAC-based variants of 4-PAM links and PNoCs with the conventional OOK links and PNoCs in terms of performance and energy efficiency in the presence of inter-channel crosstalk. From our link-level and PNoC-level evaluation, we have observed that the 4-PAM EDAC–based variants of photonic links and PNoCs exhibit better performance and energy efficiency compared with the OOK-, 4-PAM SS–, and 4-PAM ODAC–based links and PNoCs.« less
  3. This paper compares three different dc-dc topologies, i.e. boost converter, three-level flying capacitor multilevel converter (FCMC) and one-cell switching tank converter (STC) for a 100 kW electric vehicle power electronic system. This bidirectional dc-dc converter targets 300 V - 600 V voltage conversion. Total semiconductor loss index (TSLI) has been proposed to evaluate topologies and device technologies. The boost converter and one-cell STC have been fairly compared by utilizing this index. The simulation results of a 100 kW one-cell STC working at zero current switching (ZCS) mode have been provided. A 100 kW hardware prototype using 1200 V 600 Amore »SiC power module has been built. The estimated efficiency is about 99.2% at 30 kW, 99.13% at half load, and 98.64% at full load. The power density of the main circuits is about 42 kW/L« less
  4. This paper presents the integration of an AC-DC rectifier and a DC-DC boost converter circuit designed in 180 nm CMOS process for ultra-low frequency (<; 10 Hz) energy harvesting applications. The proposed rectifier is a very low voltage CMOS rectifier circuit that rectifies the low-frequency signal of 100-250 mV amplitude and 1-10 Hz frequency into DC voltage. In this work, the energy is harvested from the REWOD (reverse electrowetting-on-dielectric) generator, which is a reverse electrowetting technique that converts mechanical vibrations to electrical energy. The objective is to develop a REWOD-based self-powered motion (such as walking, running, jogging, etc.) tracking sensorsmore »that can be worn, thus harvesting energy from regular activities. To this end, the proposed circuits are designed in such a way that the output from the REWOD is rectified and regulated using a DC-DC converter which is a 5-stage cross-coupled switching circuit. Simulation results show a voltage range of 1.1 V-2.1 V, i.e., 850-1200% voltage conversion efficiency (VCE) and 30% power conversion efficiency (PCE) for low input signal in the range 100-250 mV in the low-frequency range. This performance verifies the integration of the rectifier and DC-DC boost converter which makes it highly suitable for various motion-based energy harvesting applications.« less
  5. There is an ongoing trend to increasingly offload inference tasks, such as CNNs, to edge devices in many IoT scenarios. As energy harvesting is an attractive IoT power source, recent ReRAM-based CNN accelerators have been designed for operation on harvested energy. When addressing the instability problems of harvested energy, prior optimization techniques often assume that the load is fixed, overlooking the close interactions among input power, computational load, and circuit efficiency, or adapt the dynamic load to match the just-in-time incoming power under a simple harvesting architecture with no intermediate energy storage. Targeting a more efficient harvesting architecture equipped withmore »both energy storage and energy delivery modules, this paper is the first effort to target whole system, end-to-end efficiency for an energy harvesting ReRAM-based accelerator. First, we model the relationships among ReRAM load power, DC-DC converter efficiency, and power failure overhead. Then, a maximum computation progress tracking scheme ( MaxTracker ) is proposed to achieve a joint optimization of the whole system by tuning the load power of the ReRAM-based accelerator. Specifically, MaxTracker accommodates both continuous and intermittent computing schemes and provides dynamic ReRAM load according to harvesting scenarios. We evaluate MaxTracker over four input power scenarios, and the experimental results show average speedups of 38.4%/40.3% (up to 51.3%/84.4%), over a full activation scheme (with energy storage) and order-of-magnitude speedups over the recently proposed (energy storage-less) ResiRCA technique. Furthermore, we also explore MaxTracker in combination with the Capybara reconfigurable capacitor approach to offer more flexible tuners and thus further boost the system performance.« less