Liu, Xiao, Zhou, Minxuan, Ausavarungnirun, Rachata, Eilert, Sean, Akel, Ameen, Rosing, Tajana, Narayanan, Vijaykrishnan, and Zhao, Jishen. FPRA: A Fine-grained Parallel RRAM Architecture. Retrieved from https://par.nsf.gov/biblio/10297874. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) . Web. doi:10.1109/ISLPED52811.2021.9502474.

Liu, Xiao, Zhou, Minxuan, Ausavarungnirun, Rachata, Eilert, Sean, Akel, Ameen, Rosing, Tajana, Narayanan, Vijaykrishnan, & Zhao, Jishen. FPRA: A Fine-grained Parallel RRAM Architecture. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), (). Retrieved from https://par.nsf.gov/biblio/10297874. https://doi.org/10.1109/ISLPED52811.2021.9502474

Liu, Xiao, Zhou, Minxuan, Ausavarungnirun, Rachata, Eilert, Sean, Akel, Ameen, Rosing, Tajana, Narayanan, Vijaykrishnan, and Zhao, Jishen. "FPRA: A Fine-grained Parallel RRAM Architecture". ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) (). Country unknown/Code not available. https://doi.org/10.1109/ISLPED52811.2021.9502474. https://par.nsf.gov/biblio/10297874.

@article{osti_10297874,
place = {Country unknown/Code not available}, title = {FPRA: A Fine-grained Parallel RRAM Architecture}, url = {https://par.nsf.gov/biblio/10297874}, DOI = {10.1109/ISLPED52811.2021.9502474}, abstractNote = {}, journal = {ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)}, author = {Liu, Xiao and Zhou, Minxuan and Ausavarungnirun, Rachata and Eilert, Sean and Akel, Ameen and Rosing, Tajana and Narayanan, Vijaykrishnan and Zhao, Jishen}, editor = {null} }