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Title: Scalable yet Rigorous Floating-Point Error Analysis
Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification, and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators—barely enough for HPC. In this work, we offer an approach embedded in a new tool called SATIRE that scales error analysis by four orders of magnitude compared to today’s best-of-class tools. We explain how three key ideas underlying SATIRE helps it attain such scale: path strength reduction, bound optimization, and abstraction. SATIRE provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication, and PDE stencils.  more » « less
Award ID(s):
1704715
PAR ID:
10304330
Author(s) / Creator(s):
; ; ; ;
Date Published:
Journal Name:
SC '20: The International Conference for High Performance Computing, Networking, Storage and Analysis
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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