Zhang, Zhiming, Miketic, Ivan, Salman, Emre, and Yu, Qiaoyan. Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking. Retrieved from https://par.nsf.gov/biblio/10314253. Proceedings of the 2021 on Great Lakes Symposium on VLSI . Web. doi:10.1145/3453688.3461508.
Zhang, Zhiming, Miketic, Ivan, Salman, Emre, & Yu, Qiaoyan. Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking. Proceedings of the 2021 on Great Lakes Symposium on VLSI, (). Retrieved from https://par.nsf.gov/biblio/10314253. https://doi.org/10.1145/3453688.3461508
Zhang, Zhiming, Miketic, Ivan, Salman, Emre, and Yu, Qiaoyan.
"Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking". Proceedings of the 2021 on Great Lakes Symposium on VLSI (). Country unknown/Code not available. https://doi.org/10.1145/3453688.3461508.https://par.nsf.gov/biblio/10314253.
@article{osti_10314253,
place = {Country unknown/Code not available},
title = {Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking},
url = {https://par.nsf.gov/biblio/10314253},
DOI = {10.1145/3453688.3461508},
abstractNote = {},
journal = {Proceedings of the 2021 on Great Lakes Symposium on VLSI},
author = {Zhang, Zhiming and Miketic, Ivan and Salman, Emre and Yu, Qiaoyan},
}
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