With the expansion of sensor nodes to newer avenues of technologies, such as the Internet of things (IoT), internet of bodies (IoB), augmented reality (AR), and mixed reality, the demand to support high-speed operations, such as audio and video, with a minimal increase in power consumption is gaining much traction. In this work, we focus on these nodes operating in audio-based AR (AAR) and explore the opportunity of supporting audio at a low power budget. For sensor nodes, communicating one bit of data usually consumes significantly higher power than the power associated with sensing and processing/computing one data bit. Compressing the number of communication bits at the expense of a few computation cycles considerably reduces the overall power consumption of the nodes. Audio codecs such as AAC and LDAC that currently perform compression and decompression of audio streams burn significant power and create a floor to the minimum power possible in these applications. Compressive sensing (CS), a powerful mathematical tool for compression, is often used in physiological signal sensing, such as EEG and ECG, and it can offer a promising low-power alternative to audio codecs. We introduce a new paradigm of using the CS-based approach to realize audio compression that can function as a new independent technique or augment the existing codecs for a higher level of compression. This work, CS-Audio, fabricated in TSMC 65-nm CMOS technology, presents the first CS-based compression, equipped with an ON-chip DWT sparsifier for non-sparse audio signals. The CS design, realized in a pipelined architecture, achieves high data rates and enables a wake-up implementation to bypass computation for insignificant input samples, reducing the power consumption of the hardware. The measurement results demonstrate a 3X-15X reduction in transmitted audio data without a perceivable degradation of audio quality, as indicated by the perceptual evaluation of audio quality mean opinion score (PEAQ MOS) >1.5. The hardware consumes 238 μW power at 0.65 V and 15 Mbps, which is (~20X-40X) lower than audio codecs.
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A 16 pJ/bit 0.1-15Mbps Compressive Sensing IC with on-chip DWT Sparsifier for Audio Signals
The emergence of Audio-based Augmented Reality has been calling for increasing data-rates for audio signals, with significant reduction in power to enable extremely energy-constrained sensor nodes. Typically, the communication power dominates sensing and computing power in a node [1]. For highly energy constrained scenarios, compressive sensing (CS) have been demonstrated (Fig. 1), where samples are first compressed at the sensor to contain the same information in a smaller number of samples, before transmitting to a receiver, where the signal is reconstructed. Previous CS works [2]-[5] have focused entirely on “sparse” physiological signals, operating in low speed regime. This work illustrates the first CS design, enabled with a discrete wavelet transform (DWT) sparsifier for catering to non-sparse signals such as high definition audio. Audio recording and playback are quite sensitive to quality, thereby requiring audio codecs, such as. aac, for efficient compression and decompression of audio streams, which usually consume power in the order of mW [6]. Audio inferencing operated in intelligent assistants are more tolerant to input quality, functioning effectively when the Perceptual Evaluation of Audio Quality Mean Opinion Score (PAEQ MOS) [7], an ITU-R standard objective metric for characterizing perceived audio quality, exceeds 1.5. CS presents an opportunity to achieve >10X reduction in transmitted audio data with orders of magnitude lower power, as compared to codecs. The design is implemented in 65 nm CMOS and consumes 238 uW power at 0.65 V and 15 Mbps.
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- Award ID(s):
- 1944602
- PAR ID:
- 10320902
- Date Published:
- Journal Name:
- 2021 IEEE Custom Integrated Circuits Conference (CICC)
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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