Sorting is a fundamental function in many applications
from data processing to database systems. For high performance,
sorting-hardware based sorting designs are implemented
by conventional binary or emerging stochastic computing (SC)
approaches. Binary designs are fast and energy-efficient but costly
to implement. SC-based designs, on the other hand, are area
and power-efficient but slow and energy-hungry. So, the previous
studies of the hardware-based sorting further faced scalability
issues. In this work, we propose a novel scalable low-cost design
for implementing sorting networks. We borrow the concept of SC
for the area- and power efficiency but use weighted stochastic
bit-streams to address the high latency and energy consumption
issue of SC designs. A new lock and swap (LAS) unit is proposed
to sort weighted bit-streams. The LAS-based sorting network can
determine the result of comparing different input values early and
then map the inputs to the corresponding outputs based on shorter
weighted bit-streams. Experimental results show that the proposed
design approach achieves much better hardware scalability than
prior work. Especially, as increasing the number of inputs, the
proposed scheme can reduce the energy consumption by about
3.8% - 93% compared to prior binary and SC-based designs.
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Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction
Ever-growing edge applications often require short processing latency and high energy efficiency to meet strict timing and power budget. In this work, we propose that the compact long short-term memory (LSTM) model can approximate conventional acausal algorithms with reduced latency and improved efficiency for real-time causal prediction, especially for the neural signal processing in closed-loop feedback applications. We design an LSTM inference accelerator by taking advantage of the fine-grained parallelism and pipelined feedforward and recurrent updates. We also propose a bit-sparse quantization method that can reduce the circuit area and power consumption by replacing the multipliers with the bit-shift operators. We explore different combinations of pruning and quantization methods for energy-efficient LSTM inference on datasets collected from the electroencephalogram (EEG) and calcium image processing applications. Evaluation results show that our proposed LSTM inference accelerator can achieve 1.19 GOPS/mW energy efficiency. The LSTM accelerator with 2-sbit/16-bit sparse quantization and 60% sparsity can reduce the circuit area and power consumption by 54.1% and 56.3%, respectively, compared with a 16-bit baseline implementation.
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- Award ID(s):
- 1707408
- NSF-PAR ID:
- 10337228
- Date Published:
- Journal Name:
- ACM Transactions on Design Automation of Electronic Systems
- Volume:
- 27
- Issue:
- 5
- ISSN:
- 1084-4309
- Page Range / eLocation ID:
- 1 to 19
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1145/3495006
