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Title: Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA
Award ID(s):
1911229 2009057
PAR ID:
10339671
Author(s) / Creator(s):
; ;
Date Published:
Journal Name:
IEEE High Performance Extreme Computing Conference, 2021
Page Range / eLocation ID:
1 to 7
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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