Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy.
Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction.
Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices.
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Bottom-up nanoscale patterning and selective deposition on silicon nanowires
Abstract We demonstrate a bottom-up process for programming the deposition of coaxial thin films aligned to the underlying dopant profile of semiconductor nanowires. Our process synergistically combines three distinct methods—vapor–liquid–solid nanowire growth, selective coaxial lithography via etching of surfaces (SCALES), and area-selective atomic layer deposition (AS-ALD)—into a cohesive whole. Here, we study ZrO 2 on Si nanowires as a model system. Si nanowires are first grown with an axially modulated n-Si/i-Si dopant profile. SCALES then yields coaxial poly(methyl methacrylate) (PMMA) masks on the n-Si regions. Subsequent AS-ALD of ZrO 2 occurs on the exposed i-Si regions and not on those masked by PMMA. We show the spatial relationship between nanowire dopant profile, PMMA masks, and ZrO 2 films, confirming the programmability of the process. The nanoscale resolution of our process coupled with the plethora of available AS-ALD chemistries promises a range of future opportunities to generate structurally complex nanoscale materials and electronic devices using entirely bottom-up methods.
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- Award ID(s):
- 1916953
- NSF-PAR ID:
- 10341680
- Date Published:
- Journal Name:
- Nanotechnology
- Volume:
- 33
- Issue:
- 10
- ISSN:
- 0957-4484
- Page Range / eLocation ID:
- 105604
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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Nanoimprinting has been applied in many micro- and nanoscale engineered devices; applications include displays, organic electronics, photovoltaics, optical films, and optoelectronics; and in some cases, direct imprinting of functional polymeric devices. Applications in the photonics area can significantly relieve the stringent requirement needed for nanoelectronics. We provide examples of structural colors and optical meta-surfaces facilitated by nanoimprinting, as well as plasmonic lithography masks that can produce deep-subwavelength structures using ordinary UV light. Inkjet printing has been widely used in many applications, but still faces challenges in pattern precision and feature variations. Combining Nanoimprint for patterning and inkjet printing for material deposition will take the advantage of what both technologies can offer, and can provide a high precision additive manufacturing process. We will show printed photonic devices, e.g. electro-optic polymer based optical modulators. To extend nanoimprinting to solid materials other than polymeric films will require innovative and non-conventional approaches. One such process is Metal-assisted chemical (Mac) imprint, which combines MacEtch and nanoiprint and enables direct MacEtch of Si substrate using a hybrid imprinting mold having noble metal mask. However, only low aspect ratio structures have been obtained because of the mass-transport limitation in the previous molds. Recently we effectively solved this problem by a using a specially made mold of Pt-coated anodized aluminum oxide (AAO) membrane, where the holes through the entire thickness drastically enhances the mass-transport. As a result, very high aspect ratio Si nanowires were achieved by MacImprint.more » « less
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Recent developments in inherently selective atomic layer deposition (ISALD) resulted in the deposition of amorphous ZrO2thin film on Si with a high growth rate (2 Å/cycle). The deposited film with a high dielectric constant via ISALD may be used in semiconductor processing. However, the amorphous nature of the film and the ZrO2–SiO2/Si interface must be assessed to ensure the prevention of leakage current. There is little information available in the literature regarding the ZrO2–SiO2/Si interface of atomic layer deposition (ALD) ZrO2film. In this study, high‐resolution transmission electron microscopy was extensively used to determine whether the film and the interface were crystalline or amorphous. It was interesting to find that a high‐energy electron beam can induce crystallinity in the amorphous as‐deposited ZrO2film within minutes of exposure. Moreover, outward diffusion of the nucleated tetragonal ZrO2away from the interface was also observed.
- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1088/1361-6528/ac3bed
