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1. A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training

   https://doi.org/10.1109/CICC48029.2020.9075910  

   Wei, Yijie; Cao, Qiankai; Otseidu, Kofi; Hargrove, Levi; Gu, Jie (March 2020, Custom Integrated Circuits Conference)

   An ultra-low-power gesture and gait classification SoC is presented for rehabilitation application featuring (1) mixed-signal feature extraction and integrated low-noise amplifier eliminating expensive ADC and digital feature extraction, (2) an integrated distributed deep neural network (DNN) ASIC supporting a scalable multi-chip neural network for sensor fusion with distortion resiliency for low-cost front end modules, (3) onchip learning of DNN engine allowing in-situ training of user specific operations. A 12-channel 65nm CMOS test chip was fabricated with 1μW power per channel, less than 3ms computation latency, on-chip training for user-specific DNN model and multi-chip networking capability. 

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2. Building Scalable Silicon Microring Resonator‐Based Neuromorphic Photonic Circuits Using Post‐Fabrication Processing with Photochromic Material

   https://doi.org/10.1002/adom.202402706  

   Xu, Lei; Zhang, Jiawei; Doris, Eli A; Bilodeau, Simon; Wisch, Jesse A; Gui, Manting; Jimoh, Yusuf O; Shastri, Bhavin; Rand, Barry P; Prucnal, Paul R (April 2025, Advanced Optical Materials)

   Abstract Neuromorphic photonics has become one of the research forefronts in photonics, with its benefits in low‐latency signal processing and potential in significant energy consumption reduction when compared with digital electronics. With artificial intelligence (AI) computing accelerators in high demand, one of the high‐impact research goals is to build scalable neuromorphic photonic integrated circuits which can accelerate the computing of AI models at high energy efficiency. A complete neuromorphic photonic computing system comprises seven stacks: materials, devices, circuits, microarchitecture, system architecture, algorithms, and applications. Here, we consider microring resonator (MRR)‐based network designs toward building scalable silicon integrated photonic neural networks (PNN), and variations of MRR resonance wavelength from the fabrication process and their impact on PNN scalability. Further, post‐fabrication processing using organic photochromic layers over the silicon platform is shown to be effective for trimming MRR resonance wavelength variation, which can significantly reduce energy consumption from the MRR‐based PNN configuration. Post‐fabrication processing with photochromic materials to compensate for the variation in MRR fabrication will allow a scalable silicon system on a chip without sacrificing today's performance metrics, which will be critical for the commercial viability and volume production of large‐scale silicon photonic circuits. 

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3. Polylithic Integration for RF/MM-Wave Chiplets using Stitch-Chips: Modeling, Fabrication, and Characterization

   https://doi.org/10.1109/IMS30576.2020.9223887  

   Zheng, T.; Jo, P.; Rajan, S.; Bakir, M. (January 2020, IEEE MTT-S Int. Microw. Symp. (IMS))

   A polylithic integration technology is demonstrated for seamless stitching of RF and digital chiplets. In this technology, stitch-chips with compressible microinterconnects (CMIs) are used for low-loss and dense interconnection between chiplets. A testbed using fused-silica stitch-chips with integrated CMIs is demonstrated including modeling, fabrication, assembly, and characterization. A 500 µm-long stitch-chip signal link is measured to have less than 0.4 dB insertion loss up to 30 GHz. A simulated eye diagram for 1000 µm-long stitch-chip signal link has a clear opening at 50 Gbps data rate. Moreover, the S-parameters of the CMIs are extracted from this testbed and show less than 0.17 dB insertion loss up to 30 GHz. Benchmarking to silicon interposer based interconnection is also reported. 

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4. Massively scalable wavelength diverse integrated photonic linear neuron

   https://doi.org/10.1088/2634-4386/ac8ecc  

   van Niekerk, Matthew; Rizzo, Anthony; Rubio, Hector; Leake, Gerald; Coleman, Daniel; Tison, Christopher; Fanto, Michael; Bergman, Keren; Preble, Stefan (September 2022, Neuromorphic Computing and Engineering)

   Abstract As computing resource demands continue to escalate in the face of big data, cloud-connectivity and the internet of things, it has become imperative to develop new low-power, scalable architectures. Neuromorphic photonics, or photonic neural networks, have become a feasible solution for the physical implementation of efficient algorithms directly on-chip. This application is primarily due to the linear nature of light and the scalability of silicon photonics, specifically leveraging the wide-scale complementary metal-oxide-semiconductor manufacturing infrastructure used to fabricate microelectronics chips. Current neuromorphic photonic implementations stem from two paradigms: wavelength coherent and incoherent. Here, we introduce a novel architecture that supports coherent and incoherent operation to increase the capability and capacity of photonic neural networks with a dramatic reduction in footprint compared to previous demonstrations. As a proof-of-principle, we experimentally demonstrate simple addition and subtraction operations on a foundry-fabricated silicon photonic chip. Additionally, we experimentally validate an on-chip network to predict the logical 2 bit gates AND, OR, and XOR to accuracies of 96.8%, 99%, and 98.5%, respectively. This architecture is compatible with highly wavelength parallel sources, enabling massively scalable photonic neural networks. 

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5. Creating a Backscattering Side Channel to Enable Detection of Dormant Hardware Trojans

   N. Nguyen, C. Cheng (July 2019, IEEE transactions on very large scale integration (VLSI) systems)

   Thispaperdescribesanewphysicalsidechannel,i.e. the backscattering side channel, that is created by transmitting a signal toward the IC, where the internal impedance changes caused by on-chip switching activity modulate the signal that is backscattered (reflected) from the IC. To demonstrate how this new side-channel can be used to detect small changes in circuit impedances, we propose a new method for nondestructively detecting hardware Trojans (HTs) from outside of the chip. We experimentally confirm, using measurements on one physical instance for training and nine other physical instances for testing, that the new side-channel, when combined with an HT detection method, allows detection of a dormant HT in 100% of the HT-afflicted measurements for a number of different HTs, while producing no false positives in HT free measurements. Furthermore, additional experiments are conducted to compare the backscattering-based detection to one that uses the traditional EM-emanation-based side channel. These results show that backscattering-based detection outperforms the EM side channel, confirm that dormant HTs are much more difficult for detection than HTs that have been activated, and show how detection is affected by changing the HT’s size and physical location on the IC. 

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