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A 4-channel code-multiplexed digital receiver is presented for multiple-input-multiple-output (MIMO) applications targeting 5G millimeter-wave (mm-Wave) communications. The receiver employs a code-multiplexing (CM) topology where multiple channels are encoded with unique orthogonal Walsh Hadamard codes and multiplexed into a single-channel for digitization. This approach overcomes the bottleneck of hardware complexity, cost, and power consumption in traditional multiplexing topologies by employing a single wideband analog-to-digital converter (ADC) to serve several channels. The article presents an end-to-end testbed to demonstrate the effectiveness of the proposed Code-Multiplexed Digital Receiver (CMDR) that consists of l ) ultrawideband (UWB) tightly-coupled dipole array (TCDA), 2) a custom-designed encoder circuit board (ECB), and 3) a Radio-Frequency System-on-Chip (RFSoC) field programmable gate array (FPGA) for encoding and decoding. The code sequences were generated at a maximum clock frequency of 400 MHz. Extensive experimental measurements were performed and test results were validated using performance metrics such as normalized mean square error (NMSE) and adjacent channel interference (ACI). Test results showed ACI of >20 dB, NMSE = -24.592 dB and little or no degradation in signal-to-noise ratio (SNR). To the best of our knowledge, this is the highest clock frequency and ACI value for hardware validation of channel multiplexing scheme reported in the literature.
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Synthesis of Clock Networks with a Mode-Reconfigurable Topology
Modern digital circuits are often required to operate in multiple modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized, meeting different timing constraints in different operational modes. The overall power consumption and robustness to variations of a clock network are determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that timing constraints in low- and high-performance modes can be very different. In this article, we propose a clock network with a mode-reconfigurable topology (MRT) for circuits with positive-edge-triggered sequential elements. In high-performance modes, the MRT structure is reconfigured into a near-tree to provide the required robustness to variations. In low-performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Hence, the MRT structures consume no short-circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure an MRT structure into a tree topology using a single clock gate. In high-performance modes, the experimental results demonstrate that MRT structures have \( 25\% \) lower power consumption than state-of-the-art near-tree structures. In low-performance modes, the power consumption of the MRT structure is similar to the power consumption of a clock tree.
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- Award ID(s):
- 1755825
- PAR ID:
- 10351074
- Date Published:
- Journal Name:
- ACM Transactions on Design Automation of Electronic Systems
- Volume:
- 27
- Issue:
- 4
- ISSN:
- 1084-4309
- Page Range / eLocation ID:
- 1 to 22
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1145/3503538
