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1. EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications

   Emmert, John Martin; VanDewerker, Sara A. (July 2021, 64th IEEE International Midwest Symposium on Circuits and Systems)

   null (Ed.)

   A Muller C-Element is a digital circuit component used in most asynchronous circuits and systems. In Null Convention Logic, the Muller C-Elements make up the subset of THmn threshold gates where the threshold, m, and the input bit- width, n, are equal. This paper presents a new Efficient Muller C- Element implementation, EMC, that is especially suitable for Null Convention Logic applications with high input bit-widths, and it is much faster and smaller than standard implementations. It has a two-transistor switching delay that is independent of the input bit- width, n, and exhibits low noise and static power consumption. It is suitable for all Muller C-Element applications, especially those like Null Convention Logic register feedback circuits that can have large input bit-widths. To reduce static power consumption, it uses active resistors that are only turned “ON” when necessary. Two output stages are presented to implement the required Muller C- Element digital hysteresis: standard, semi-static cross-coupled inverter version, and differential sense-amplifier option. For large values of n, our circuit requires approximately one-half fewer transistors than combining smaller Null Convention Logic THmn semi-static threshold gates. We have successfully simulated up to n = 1024 at a 65 nm node. 

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2. Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits

   https://doi.org/10.1109/SOCC.2018.8618494  

   Sharma, N.; Binek, C.; Marshall, A.; Bird, J. P.; Dowben, P. A.; Nikonov, D. (January 2019, 2018 31st IEEE International System-on-Chip Conference (SOCC))

   A Verilog-A based model for the magneto-electric field effect transistor (MEFET) device is implemented and a variety of logic functions based on this device are proposed. These models are used to capture energy consumption and delay per switching event and to benchmark the MEFET with respect to CMOS. Single-source MEFET devices can be used for conventional logic gates like NAND, NOR, inverter and buffer and more complex circuits like the full adder. The dual source MEFET is an enhanced version of the MEFET device which functions like a spin multiplexer (spin-MUXer). Circuits using MEFETs require fewer components than CMOS to generate the same logic operation. These devices display a high on-off ratio., unlike many magneto-electric devices., and they operate at very low voltages., resulting in lower switching energy. Benchmarking results show that these devices perform better in terms of energy and delay., for implementing more complex functions., than the basic logic gates. 

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3. Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration

   Miketic, Ivan; Salman, Emre (September 2020, IEEE International System-on-Chip Conference (SOCC))

   Charge-recycling adiabatic circuits are recently receiving increased attention due to both high energy-efficiency and higher resistance against side-channel attacks. These characteristics make adiabatic circuits a promising technique for Internet-of-things based applications. One of the important limitations of adiabatic logic is the higher intra-cell interconnect capacitance due to differential outputs and cross-coupled pMOS transistors. Since energy consumption has quadratic dependence on capacitance in adiabatic circuits (unlike conventional static CMOS where dependence is linear), higher interconnect capacitance significantly degrades the overall power savings that can be achieved by adiabatic logic, particularly in nanoscale technologies. In this paper, monolithic 3D integrated adiabatic circuits are introduced where transistor-level monolithic 3D technology is used to implement adiabatic gates. A 45 nm two-tier Mono3D PDK is used to demonstrate the proposed approach. Monolithic inter-tier vias are leveraged to significantly reduce parasitic interconnect capacitance, achieving up to 47% reduction in power-delay product as compared to 2D adiabatic circuits in a 45 nm technology node. 

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4. Comparison of Hafnium Dioxide and Zirconium Dioxide Grown by Plasma-Enhanced Atomic Layer Deposition for the Application of Electronic Materials

   https://doi.org/10.3390/cryst10020136  

   Xiao, Zhigang; Kisslinger, Kim; Chance, Sam; Banks, Samuel (February 2020, Crystals)

   We report the growth of nanoscale hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) thin films using remote plasma-enhanced atomic layer deposition (PE-ALD), and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using the HfO2 and ZrO2 thin films as the gate oxide. Tetrakis (dimethylamino) hafnium (Hf[N(CH3)2]4) and tetrakis (dimethylamino) zirconium (IV) (Zr[N(CH3)2]4) were used as the precursors, while O2 gas was used as the reactive gas. The PE-ALD-grown HfO2 and ZrO2 thin films were analyzed using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). The XPS measurements show that the ZrO2 film has the atomic concentrations of 34% Zr, 2% C, and 64% O while the HfO2 film has the atomic concentrations of 29% Hf, 11% C, and 60% O. The HRTEM and XRD measurements show both HfO2 and ZrO2 films have polycrystalline structures. n-channel and p-channel metal-oxide semiconductor field-effect transistors (nFETs and pFETs), CMOS inverters, and CMOS ring oscillators were fabricated to test the quality of the HfO2 and ZrO2 thin films as the gate oxide. Current-voltage (IV) curves, transfer characteristics, and oscillation waveforms were measured from the fabricated transistors, inverters, and oscillators, respectively. The experimental results measured from the HfO2 and ZrO2 thin films were compared. 

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5. MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA

   https://doi.org/10.1109/TVLSI.2025.3539670  

   Nasab, Milad Tanavardi; Thapliyal, Himanshu; Rose, Garrett S (May 2025, IEEE Transactions on Very Large Scale Integration (VLSI) Systems)

   Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages. 

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