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Title: LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection
In this work, we propose LUT-Lock, a novel Look-Up-Table-based netlist obfuscation algorithm, for protecting the intellectual property that is mapped to an FPGA bitstream or an ASIC netlist. We, first, illustrate the effectiveness of several key features that make the LUT-based obfuscation more resilient against SAT attacks and then we embed the proposed key features into our proposed LUT-Lock algorithm. We illustrate that LUT-Lock maximizes the resiliency of the LUT-based obfuscation against SAT attacks by forcing a near exponential increase in the execution time of a SAT solver with respect to the number of obfuscated gates. Hence, by adopting LUT-Lock algorithm, SAT attack execution time could be made unreasonably long by increasing the number of utilized LUTs.  more » « less
Award ID(s):
2200446
PAR ID:
10360788
Author(s) / Creator(s):
; ; ; ;
Date Published:
Journal Name:
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Page Range / eLocation ID:
405 to 410
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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