Tunneling field effect transistors (TFETs) have gained much interest in the previous decade for use in low power CMOS electronics due to their sub-thermal switching [1]. To date, all TFETs are fabricated as vertical nanowires or fins with long, difficult processes resulting in long learning cycle and incompatibility with modern CMOS processing. Because most TFETs are heterojunction TFETs (HJ-TFETs), the geometry of the device is inherently vertically because dictated by the orientation of the tunneling HJ, achieved by typical epitaxy.
Template assisted selective epitaxy was demonstrated for vertical nanowires [2] and horizontally arranged nanorods [3] for III-V on Si integration. In this work, we report results on the area selective and template assisted epitaxial growth of InP, utilizing SiO2 based confined structures on InP substrates, which enables horizontal HJs, that can find application in the next generation of TFET devices. The geometries of the confined structures used are so that only a small area of the InP substrate, dubbed seed, is visible to the growth atmosphere. Growth is initiated selectively only at the seed and then proceeds in the hollow channel towards the source hole. As a result, growth resembles epitaxial lateral overgrowth from a single nucleation point [4], reaping the benefits of defect confinement and, contrary to spontaneous nanowire growth, allows orientation in an arbitrary, template defined direction.
Indium phosphide 2-inch (110) wafers are used as the starting substrate. The process flow (Fig.1) consists of two plasma enhanced chemical vapor deposition (PECVD) steps of SiO2, appropriately patterned with electron beam lithography (EBL), around a PECVD amorphous silicon sacrificial layer. The sacrificial layer is ultimately wet etched with XeF2 to form the final, channel like template. Not shown in the schematic in Fig.1 is an additional, ALD deposited, 3 nm thick, alumina layer which prevents plasma damage to the starting substrate and is removed via a final tetramethylammonium hydroxide (TMAH) based wet etch. As-processed wafers were then diced and loaded in a Thomas Swan Horizontal reactor. Successful growth conditions found were 600°C with 4E6 mol/min of group III precursor, a V/III ratio of 400 and 8 lpm of hydrogen as carrier gas. Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as In and P precursors respectively. Top view SEM (Fig.2) confirms growth in the template thanks to sufficient Z-contrast despite the top oxide layer, not removed before imaging. TEM imaging shows a cross section of the confined structure taken at the seed hole (Fig.3). The initial growth interface suggests growth was initiated at the seed hole and atomic order of the InP conforms to the SiO2 template both at the seed and at the growth front. A sharp vertical facet is an encouraging result for the future development of vertical HJ based III-V semiconductor devices.
more »
« less
Suspension and transfer printing of ZnCdMgSe membranes from an InP substrate
Wide bandgap II-VI semiconductors, lattice-matched to InP substrates, show promise for use in novel, visible wavelength photonic devices; however, release layers for substrate removal are still under development. An under-etch method is reported which uses an InP substrate as an effective release layer for the epitaxial lift-off of lattice-matched ZnCdMgSe membranes. An array of 100-µm-square membranes is defined on a ZnCdMgSe surface using dry etching and suspended from the InP substrate using a three-step wet etch. The ZnCdMgSe membranes are transfer-printed onto a diamond heatspreader and have an RMS surface roughness < 2 nm over 400 µm2, similar to the epitaxial surface. Membranes on diamond show a photoluminescence peak at ∼520 nm and a thermal redshift of 4 nm with ∼3.6 MWm−2continuous optical pumping at 447 nm. Effective strain management during the process is demonstrated by the absence of cracks or visible membrane bowing and the high brightness photoluminescence indicates a minimal non-radiative defect introduction. The methodology presented will enable the heterogeneous integration and miniaturization of II-VI membrane devices.
more » « less- NSF-PAR ID:
- 10371872
- Publisher / Repository:
- Optical Society of America
- Date Published:
- Journal Name:
- Optical Materials Express
- Volume:
- 10
- Issue:
- 12
- ISSN:
- 2159-3930
- Page Range / eLocation ID:
- Article No. 3328
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
more » « less
Abstract Strain engineering in perovskite oxides provides for dramatic control over material structure, phase, and properties, but is restricted by the discrete strain states produced by available high‐quality substrates. Here, using the ferroelectric BaTiO3, production of precisely strain‐engineered, substrate‐released nanoscale membranes is demonstrated via an epitaxial lift‐off process that allows the high crystalline quality of films grown on substrates to be replicated. In turn, fine structural tuning is achieved using interlayer stress in symmetric trilayer oxide‐metal/ferroelectric/oxide‐metal structures fabricated from the released membranes. In devices integrated on silicon, the interlayer stress provides deterministic control of ordering temperature (from 75 to 425 °C) and releasing the substrate clamping is shown to dramatically impact ferroelectric switching and domain dynamics (including reducing coercive fields to <10 kV cm−1and improving switching times to <5 ns for a 20 µm diameter capacitor in a 100‐nm‐thick film). In devices integrated on flexible polymers, enhanced room‐temperature dielectric permittivity with large mechanical tunability (a 90% change upon ±0.1% strain application) is demonstrated. This approach paves the way toward the fabrication of ultrafast CMOS‐compatible ferroelectric memories and ultrasensitive flexible nanosensor devices, and it may also be leveraged for the stabilization of novel phases and functionalities not achievable via direct epitaxial growth.
-
more » « less
Abstract In thermionic energy converters, the absolute efficiency can be increased up to 40% if space-charge losses are eliminated by using a sub-10-µm gap between the electrodes. One practical way to achieve such small gaps over large device areas is to use a stiff and thermally insulating spacer between the two electrodes. We report on the design, fabrication and characterization of thin-film alumina-based spacers that provided robust 3–8 μm gaps between planar substrates and had effective thermal conductivities less than those of aerogels. The spacers were fabricated on silicon molds and, after release, could be manually transferred onto any substrate. In large-scale compression testing, they sustained compressive stresses of 0.4–4 MPa without fracture. Experimentally, the thermal conductance was 10–30 mWcm−2K−1and, surprisingly, independent of film thickness (100–800 nm) and spacer height. To explain this independence, we developed a model that includes the pressure-dependent conductance of locally distributed asperities and sparse contact points throughout the spacer structure, indicating that only 0.1–0.5% of the spacer-electrode interface was conducting heat. Our spacers show remarkable functionality over multiple length scales, providing insulating micrometer gaps over centimeter areas using nanoscale films. These innovations can be applied to other technologies requiring high thermal resistance in small spaces, such as thermophotovoltaic converters, insulation for spacecraft and cryogenic devices.
-
2D materials-assisted heterogeneous integration of semiconductor membranes toward functional devicesHeterogeneous integration techniques allow the coupling of highly lattice-mismatched solid-state membranes, including semiconductors, oxides, and two-dimensional materials, to synergistically fuse the functionalities. The formation of heterostructures generally requires two processes: the combination of crystalline growth and a non-destructive lift-off/transfer process enables the formation of high-quality heterostructures. Although direct atomic interaction between the substrate and the target membrane ensures high-quality growth, the strong atomic bonds at the substrate/epitaxial film interface hinder the non-destructive separation of the target membrane from the substrate. Alternatively, a 2D material-coated compound semiconductor substrate can transfer the weakened (but still effective) surface potential field of the surface through the 2D material, allowing both high-quality epitaxial growth and non-destructive lift-off of the grown film. This Perspective reviews 2D/3D heterogeneous integration techniques, along with applications of III–V compound semiconductors and oxides. The advanced heterogeneous integration methods offer an effective method to produce various freestanding membranes for stackable heterostructures with unique functionalities that can be applied to novel electrical, optoelectronic, neuromorphic, and bioelectronic systems.more » « less
-
Room-temperature, pulsed-operation lasing of 8.5 μm-emitting InP-based quantum cascade lasers (QCLs), with low threshold-current density and watt-level output power, is demonstrated from structures grown on (001) GaAs substrates by metal-organic chemical vapor deposition. Prior to growing the laser structure, which contains a 35-stage In 0.53 Ga 0.47 As/In 0.52 Al 0.48 As lattice-matched active-core region, a ∼2 μm-thick nearly fully relaxed InP buffer with strained 1.6 nm-thick InAs quantum-dot-like dislocation-filter layers was grown. A smooth terminal buffer-layer surface, with roughness as low as 0.4 nm on a 10 × 10 μm 2 scale, was obtained, while the estimated threading-dislocation density was in the mid-range × 10 8 cm −2 . A series of measurements, on lasers grown on InP metamorphic buffer layers (MBLs) and on native InP substrates, were performed for understanding the impact of the buffer-layer's surface roughness, residual strain, and threading-dislocation density on unipolar devices such as QCLs. As-cleaved devices, grown on InP MBLs, were fabricated as 25 μm × 3 mm deep-etched ridge guides with lateral current injection. The results are pulsed maximum output power of 1.95 W/facet and a low threshold-current density of 1.86 kA/cm 2 at 293 K. These values are comparable to those obtained from devices grown on InP: 2.09 W/facet and 2.42 kA/cm 2 . This demonstrates the relative insensitivity of the device-performance metrics on high residual threading-dislocation density, and high-performance InP-based QCLs emitting near 8 μm can be achieved on lattice-mismatched substrates.more » « less
