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2. ADMM-Based Distributed DC Optimal Power Flow with Power Flow Control

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3. Ensemble Learning based Linear Power Flow

   https://doi.org/10.1109/PESGM41954.2020.9281793  

   Hu, Ren; Li, Qifeng; Lei, Shunbo (August 2020, 2020 IEEE Power & Energy Society General Meeting (PESGM))

   null (Ed.)

   This paper develops an ensemble learning-based linearization approach for power flow with reactive power modeled, where the polynomial regression (PR) is first used as a basic learner to capture the linear relationships between the bus voltages as the independent variables and the active or reactive power as the dependent variable in rectangular coordinates. Then, gradient boosting (GB) and bagging as ensemble learning methods are introduced to combine all basic learners to boost the model performance. The inferred linear power flow model is applied to solve the well-known optimal power flow (OPF) problem. The simulation results on IEEE standard power systems indicate that (1) ensemble learning methods can significantly improve the efficiency of PR, and GB works better than bagging; (2) as for solving OPF, the data-driven model outperforms the DC model and the SDP relaxation in both accuracy, and computational efficiency. 

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4. Power-based Attacks on Spatial DNN Accelerators

   https://doi.org/10.1145/3491219  

   Li, Ge; Tiwari, Mohit; Orshansky, Michael (July 2022, ACM Journal on Emerging Technologies in Computing Systems)

   With proliferation of DNN-based applications, the confidentiality of DNN model is an important commercial goal. Spatial accelerators, which parallelize matrix/vector operations, are utilized for enhancing energy efficiency of DNN computation. Recently, model extraction attacks on simple accelerators, either with a single processing element or running a binarized network, were demonstrated using the methodology derived from differential power analysis (DPA) attack on cryptographic devices. This article investigates the vulnerability of realistic spatial accelerators using general, 8-bit, number representation. We investigate two systolic array architectures with weight-stationary dataflow: (1) a 3 × 1 array for a dot-product operation and (2) a 3 × 3 array for matrix-vector multiplication. Both are implemented on the SAKURA-G FPGA board. We show that both architectures are ultimately vulnerable. A conventional DPA succeeds fully on the 1D array, requiring 20K power measurements. However, the 2D array exhibits higher security even with 460K traces. We show that this is because the 2D array intrinsically entails multiple MACs simultaneously dependent on the same input. However, we find that a novel template-based DPA with multiple profiling phases is able to fully break the 2D array with only 40K traces. Corresponding countermeasures need to be investigated for spatial DNN accelerators. 

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5. Practical and Fast Momentum-Based Power Methods

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