Pandey, Sujay, Liao, Zhiwei, Nandi, Shreyas, Natarajan, Suriyaprakash, Sinha, Arani, Singh, Adit, and Chatterjee, Abhijit. Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. Retrieved from https://par.nsf.gov/biblio/10406387. 2021 IEEE 39th VLSI Test Symposium (VTS) . Web. doi:10.1109/VTS50974.2021.9441005.

Pandey, Sujay, Liao, Zhiwei, Nandi, Shreyas, Natarajan, Suriyaprakash, Sinha, Arani, Singh, Adit, & Chatterjee, Abhijit. Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. 2021 IEEE 39th VLSI Test Symposium (VTS), (). Retrieved from https://par.nsf.gov/biblio/10406387. https://doi.org/10.1109/VTS50974.2021.9441005

Pandey, Sujay, Liao, Zhiwei, Nandi, Shreyas, Natarajan, Suriyaprakash, Sinha, Arani, Singh, Adit, and Chatterjee, Abhijit. "Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts". 2021 IEEE 39th VLSI Test Symposium (VTS) (). Country unknown/Code not available. https://doi.org/10.1109/VTS50974.2021.9441005. https://par.nsf.gov/biblio/10406387.

@article{osti_10406387,
place = {Country unknown/Code not available}, title = {Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts}, url = {https://par.nsf.gov/biblio/10406387}, DOI = {10.1109/VTS50974.2021.9441005}, abstractNote = {}, journal = {2021 IEEE 39th VLSI Test Symposium (VTS)}, author = {Pandey, Sujay and Liao, Zhiwei and Nandi, Shreyas and Natarajan, Suriyaprakash and Sinha, Arani and Singh, Adit and Chatterjee, Abhijit}, }