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Title: FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge
Award ID(s):
2008365 2132918
PAR ID:
10417060
Author(s) / Creator(s):
; ; ; ; ; ; ; ; ; ;
Date Published:
Journal Name:
IEEE Transactions on Circuits and Systems I: Regular Papers
Volume:
70
Issue:
6
ISSN:
1549-8328
Page Range / eLocation ID:
2398 to 2411
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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