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1. Progress in neuromorphic photonics

   https://doi.org/10.1515/nanoph-2016-0139  

   Ferreira de Lima, Thomas; Shastri, Bhavin J.; Tait, Alexander N.; Nahmias, Mitchell A.; Prucnal, Paul R. (January 2017, Nanophotonics)

   Abstract As society’s appetite for information continues to grow, so does our need to process this information with increasing speed and versatility. Many believe that the one-size-fits-all solution of digital electronics is becoming a limiting factor in certain areas such as data links, cognitive radio, and ultrafast control. Analog photonic devices have found relatively simple signal processing niches where electronics can no longer provide sufficient speed and reconfigurability. Recently, the landscape for commercially manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. By bridging the mathematical prowess of artificial neural networks to the underlying physics of optoelectronic devices, neuromorphic photonics could breach new domains of information processing demanding significant complexity, low cost, and unmatched speed. In this article, we review the progress in neuromorphic photonics, focusing on photonic integrated devices. The challenges and design rules for optoelectronic instantiation of artificial neurons are presented. The proposed photonic architecture revolves around the processing network node composed of two parts: a nonlinear element and a network interface. We then survey excitable lasers in the recent literature as candidates for the nonlinear node and microring-resonator weight banks as the network interface. Finally, we compare metrics between neuromorphic electronics and neuromorphic photonics and discuss potential applications. 

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2. Towards Large-Scale Photonic Neural-Network Accelerators

   https://doi.org/10.1109/IEDM19573.2019.8993624  

   Hamerly, R.; Sludds, A.; Bernstein, L.; Prabhu, M.; Roques-Carmes, C.; Carolan, J.; Yamamoto, Y.; Soljacic, M.; Englund, D. (December 2019, IEEE IEDM)

   Optical approaches to AI acceleration have gained intense interest recently due to the potentially breakthrough advantages of photonics: high bandwidth, low power consumption, and efficient data movement. We overview leading photonic AI platforms based on beamsplitter mesh networks, weight banks, and photoelectric multiplication. While the theoretical performance can be orders of magnitude beyond current state of the art, practical issues of chip area, input / output, and crosstalk paint a more nuanced near-term picture of photonic AI acceleration. Both fundamental and near-term limitations to energy efficiency are addressed, and bandwidth limitations due to temporal crosstalk are analyzed. 

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3. MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations

   Yandong Luo, Xiaochen Peng (July 2019, International Conference on Neuromorphic Systems (ICONS))

   On-chip learning with compute-in-memory (CIM) paradigm has become popular in machine learning hardware design in the recent years. However, it is hard to achieve high on-chip learning accuracy due to the high nonlinearity in the weight update curve of emerging nonvolatile memory (eNVM) based analog synapse devices. Although digital synapse devices offer good learning accuracy, the row-by-row partial sum accumulation leads to high latency. In this paper, the methods to solve the aforementioned issues are presented with a device-to-algorithm level optimization. For analog synapses, novel hybrid precision synapses with good linearity and more advanced training algorithms are introduced to increase the on-chip learning accuracy. The latency issue for digital synapses can be solved by using parallel partial sum read-out scheme. All these features are included into the recently released MLP + NeuroSimV3.0, which is an in-house developed device-to-system evaluation framework for neuro-inspired accelerators based on CIM paradigm. 

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4. A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals

   https://doi.org/10.1145/3453688.3461531  

   Yang, Mingdai; Jokar, Mohammad Reza; Qiu, Junyi; Lou, Qiuwen; Liu, Yuming; Udupa, Aditi; Chong, Frederic T.; Dallesasse, John M.; Feng, Milton; Goddard, Lynford L.; et al (July 2021, GLSVLSI '21: Proceedings of the 2021 on Great Lakes Symposium on VLSI)

   null (Ed.)

   We present a hybrid optical-electrical analog deep learning (DL) accelerator, the first work to use incoherent optical signals for DL workloads. Incoherent optical designs are more attractive than coherent ones as the former can be more easily realized in practice. However, a significant challenge in analog DL accelerators, where multiply-accumulate operations are dominant, is that there is no known solution to perform accumulation using incoherent optical signals. We overcome this challenge by devising a hybrid approach: accumulation is done in the electrical domain, while multiplication is performed in the optical domain. The key technology enabler of our design is the transistor laser, which performs electrical-to-optical and optical-to-electrical conversions efficiently to tightly integrate electrical and optical devices into compact circuits. As such, our design fully realizes the ultra high-speed and high-energy-efficiency advantages of analog and optical computing. Our evaluation results using the MNIST benchmark show that our design achieves 2214× and 65× improvements in latency and energy, respectively, compared to a state-of-the-art memristor-based analog design. 

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5. Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment

   Zhang, Jingyang; Yang, Huanrui; Chen, Fan; Wang, Yitu; Li, Hai (December 2019, The 5th Workshop on Energy Efficient Machine Learning and Cognitive Computing co-located with NeurIPS 2019)

   Emerging resistive random-access memory (ReRAM) has recently been intensively investigated to accelerate the processing of deep neural networks (DNNs). Due to the in-situ computation capability, analog ReRAM crossbars yield significant throughput improvement and energy reduction compared to traditional digital methods. However, the power hungry analog-to-digital converters (ADCs) prevent the practical deployment of ReRAM-based DNN accelerators on end devices with limited chip area and power budget. We observe that due to the limited bitdensity of ReRAM cells, DNN weights are bit sliced and correspondingly stored on multiple ReRAM bitlines. The accumulated current on bitlines resulted by weights directly dictates the overhead of ADCs. As such, bitwise weight sparsity rather than the sparsity of the full weight, is desirable for efficient ReRAM deployment. In this work, we propose bit-slice `1, the first algorithm to induce bit-slice sparsity during the training of dynamic fixed-point DNNs. Experiment results show that our approach achieves 2 sparsity improvement compared to previous algorithms. The resulting sparsity allows the ADC resolution to be reduced to 1-bit of the most significant bit-slice and down to 3-bit for the others bits, which significantly speeds up processing and reduces power and area overhead. 

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